[SI-LIST] Re: DDR-1 termination (short point-to-point)

  • From: "Novak David (TTE)" <david.novak@xxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 4 Feb 2005 10:18:16 -0500

The DDR will never be a "slow drive". However, the x32 GDDR parts do
allow more control over drive strength.

As long as you keep the lines short, you should have no problems with a
simple series resistor in each line. This is a very common termination
scheme for point-to-point DDR designs.

If it were not for the 300mV overshoot specs. on most DDR memory
controllers, you wouldn't even need the series resistors.

David


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Anders Frederiksen
Sent: Thursday, February 03, 2005 5:00 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR-1 termination (short point-to-point)


I'm connecting a lot of DDR1 ram to a FPGA (Virtex2pro). Common schemes
recommended is "embedding a DIMM design" (which would be plain stupid
imho) and doing a full parallel termination in both ends (typically in
0402). The latter is naturally sensible - but it occurs to be kind of a
overkill for ponit-to-point lines of "only" 5cm (~2") or less. Has
anyone experience with simpler termination schemes? I mean for standard
busses one would rely on slow drivers only...

Cheers,
 Anders



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