[SI-LIST] Re: DDR-1 termination (short point-to-point)
- From: "De Paepe, Kristiaan" <kristiaan.depaepe@xxxxxxxxx>
- To: "'Julia Nekrylova'" <JNEKRYLO@xxxxxxxxxx>, "De Paepe, Kristiaan" <kristiaan.depaepe@xxxxxxxxx>, af@xxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sun, 6 Feb 2005 00:25:39 +0100
Julia,
Of course this is true.
Although, wouldn't you agree that taking enough noise margin into account
(say 300mV) would cover most SSN in a properly designed PDS? (At least as
long as the FPGA doesn't bounce too much internally, one has to rely on the
compiler feedback for that information.) Sure, it (SSN) affects timing, but
if all else is fine, I believe the impact is acceptable.
Anders,
how many bits if I might ask? 256? 512? This number will probably get you in
trouble when using the SSTL2C2 on the V2P regarding the SSO number.
If my poor memory serves me well, I think the V2P is quite sensitive to
over/undershoot on its IO. (Check the datasheet and with your FAE when in
doubt.)
I once simulated a design with 5 cm lines, resulting in (for the data-lines)
just resistors at the DDR (just like Ravinder) BUT with DCI on the V2P IO
pads (mind chip dissipation though); guess this won't cut your problem
though.
As Julia and others have stated, I also prefer proper termination on DDR
interfaces; it is what the original SSTL2 spec stands for.
Kind Regards,
Kristiaan
-----Original Message-----
From: Julia Nekrylova [mailto:JNEKRYLO@xxxxxxxxxx]
Sent: 4-feb-05 21:34
To: kristiaan.depaepe@xxxxxxxxx; af@xxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: DDR-1 termination (short point-to-point)
A simple SI and timing simulation would not include SSN effects (ground
bounce, power noise) that in the presence of terminations are far more
manageable. This is just a reminder that SSN can kill DDR performance,
not just reflections and crosstalk.
Regards,
Julia
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