[SI-LIST] DDR timing equation question

Hello SI experts, 
I have to solve for a DDR interface issue when traffic is full bandwith
(1Gb/s): DDR is then blocked and we can not access to it anymore. 
Note that this "should not be" a card bug because it happens only on a
few cards. 
FYI, the Controller is an Intel Network Processor IXP2400. 
I would like to check the timing but I have to know the setup and hold
time equations. 

I found on an Intel Powerpoint the following equations, for READ access
(data from DDR to NPU): 

        * Tsetup = Tdelay - Tdqsq max + TOFdqs min - TOFdq max

        * Thold = Tqh - Tdelay + TOFdq min - TOFdq max

The file can be viewed from the following URL: 
www.ee.sc.edu/classes/Spring07/elct865/Class_Notes/ClassNotes1_Summary86
5.ppt

When we observe the waveform on slide 111, I don't understand what is
the difference between Tdelay and TOF dqs? 
Can someone explain in details how should be interpreted Tdelay and the
DDR hold time calculation in general ? 

Note that I would like to minus the ISI value on DQ data on these
equations: am I right?  

Thank you, 
Regards, 

Jean-Pierre. 



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