[SI-LIST] Re: DDR stubs and non- stuff options
- From: "Xu, Catherine (ICS)" <xu@xxxxxx>
- To: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>, Doug Brooks <dbrooks7@xxxxxxxxxx>
- Date: Fri, 8 May 2009 00:29:26 +0000
Hello Maheshwari,
I did a design using daisy chain to drive two DDR2 ( above 200 MHz ) DRAM part
on a 4-layer PCB. The part closer to the controller can be loaded or no-load.
So I believe it is feasible to implement your design to support MDDR at 133 MHz.
I agree with all the recommendations from the mail-list. Something I did to
implement the daisy chain design include:
1) use SI tool for pre-layout simulation to develop design guideline
2) strictly enforce the typical design guideline such as balancing trace
length within the DQ group. Use SI tool to understand design guideline priority
and trade-offs due to tight routing channel on 4 layer board.
3) After getting the prototype board, refine SI model with post layout
simulation to achieve correlation with the measurement on prototype board.
4) After getting correlation between simulation and measurement, use SI tool to
develop the optimized settings on driver strength, ODT, delay etc for different
read/write cases to maximize design margin. Then program the controller with
the optimized settings.
A balanced T layout daisy chain design will likely yield more timing margin
when longer stub length is needed. I opted for daisy chain with short stub to
the 1st DDR part ( longest stub length <100 mils ) instead of balanced T
because of other design constraints on component placement.
Have fun in your design !
Catherine Xu
__________________________________
Sr. HW Design Engineer, Ph.D
HP - San Diego
_________________________________
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Hermann Ruckerbauer
Sent: Thursday, May 07, 2009 8:49 AM
To: Doug Brooks
Cc: ranjith; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR stubs and non- stuff options
Hello Maheshwari,
I agree with Doug that a 0.1" stub is most likely not going to cause any
issue. I guess the double loading in the full populated case is going to
be worse in SI than the single loaded case with the stub.
In the double loading case this stub is still there. In this case you
will have the motherboard stub PLUS the DRAM Package stub (I guess this
is DDR1-266 ==> no OnDie Termination for DQ or CA) and the Cin of the
DRAM which is causing much more reflections than just the unloaded
motherboard stub in the non populated case.
regards
Hermann Ruckerbauer
www.eyeknowhow.de
Doug Brooks schrieb:
> Think in terms of the "critical length." You don't say what the rise time
> of the clock is, but at 133MHz the critical length is likely not less than
> 1.5" to 2" (quite likely more). Thus, .1" is such a small fraction of the
> critical length that the stub reflections will not be an issue.
>
> Doug Brooks
> http://www.ultracad.com
>
>
>
>
>> Thanks for the feedback.
>> We are using mobile DDR. The Maximum clock frequency is 133MHz.
>> While routing dasisy chain, we are estimating 100 mils stub in DDR(1)
>> which close to the processor (see below diagram). If we no mount this
>> DDR(1) this 100 mils additional stub will be there. Is this stub will
>> create an issue in 133MHz DDR operation?
>>
>> TLA = 1" stub = 0.1"
>> CPU ----------------o------- DDR(1)
>> |
>> TLB = 0.7" |
>> |
>> |
>> DDR(2)
>>
>> Thanks
>> Ranjith
>>
>>
>> Stubs are never a good idea. Whether your stubs will be enough to wipe
>> out your margins depends on how fast you intend to signal and what your
>> layout looks like. You should arrange your layout so that the
>> conditionally stuffed component is the middle one in the chain. Is this
>> DDR2, or DDR3?
>>
>> Steve
>>
>> maheshwari palanisamy wrote:
>>
>>> hi team,
>>> I am currently designing a processor module. In this case, I have a
>>> processor
>>> which can support 16bit DDR and supports 2 chip selects.
>>>
>>> To get the benifit of price, I am planning to use both the chipselects.
>>> But
>>> stuff only one DDR for lower memory requirements and will not stuff the
>>> second DDR. Both DDR will be stuffed only for highest memory
>>> configuration.
>>>
>>> In the case of only one DDR been stuffes, will the stubs in the DDR
>>> address &
>>> data create issue because of reflections? And Is this recommended to
>>> stuff
>>> one alone?
>>>
>>> Thanks in advance.
>>> Maheshwari
>>>
>>>
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