[SI-LIST] Re: DDR simulation

Zhanghan,

You can reduce the mismatch at the first DIMM by using a lower Zo on the
main segment trace between the controller and the 1st DIMM.  For example
you might use a wide 35-40ohm trace here, then use a standard 55-60ohm
trace between DIMMS.  This has proved to significantly improve SI on two
DIMM topologies.  I've never looked at a 4 DIMM topology myslef, but
suspect it may also help there. =20


Brian P. Moran =20
Intel Corporation=20
brian.p.moran@xxxxxxxxx=20


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Saturday, February 26, 2005 2:16 AM
To: zhang_kun@xxxxxxxxxx; si-list
Subject: [SI-LIST] Re: DDR simulation

Zhangkun, did you forget the series damping resistors?
Steve.
At 01:58 PM 2/26/2005 +0800, Zhangkun wrote:

>Dear all
>I am simulating about DDR. The topology is following:
>
>                            (800mil)
>Driver=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3Dr_pull
>            (4000mil)      |       |      |      |
>                           |       |      |      |
>                          load    load   load   load
>
>The simulaiton result shows that the waveform at the first load is very

>bad. How to improve it? The DDR is of 400MHz. The stub at near load is=20
>only 100mil.
>
>Best Regards
>
>Zhangkun
>2005.2.26
>
>
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