[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>, "'Chris.Cheng@xxxxxxxxxxxx'" <Chris.Cheng@xxxxxxxxxxxx>, "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 22 Jul 2005 13:52:49 -0700
Charles, sure.
If we back up to differential signaling, the idea is to send signal plus
noise in two forms so that the noise can be numerically subtracted out. In
a pseudo differential scheme the idea is the same, just we accept a less
accurate approximation of the noise. So, ideally we forward a "static"
signal that represents the idealized switching point of the signal. In
this case it would be the midpoint of Vddq and Vss as seen at the driver.
Chris points out immediately that this will vary across the die / package
depending on the recent history, and current data pattern. So it is hard
for such a scheme to accomodate bounce in the transmitter. It can still
have substantial value however if it subjects the switching reference to
the same channel disturbances, including the bounce of the receiver as the
data signals. So, take an image of the approximate center swing on the
signal and transmit it to the receiver. Now, our problem is what to do
with the signal at the receive end.
If we want the signal to reproduce channel effects, then we do NOT want to
swamp out the signal with a big bypass cap at the receiver. We would want
to treat the forwarded Vref as another transmission line. Ideally, we
would have used a similar drive and termination scheme as for our single
ended drivers. That can be pretty awkward, and isn't the norm.
If however, our channel is relatively well behaved, then the primary noise
we want to overcome is bounce in the receiver package. In that case
bypassing Vref to receiver Vss, and receiver Vtt to receiver Vss will
reduce some of the noise.
Regards,
Steve.
At 09:57 AM 7/22/2005 -0600, Grasso, Charles wrote:
>Hi Steve,
>
>I must admit to being totally lost with the application of a pseudo
>differential scheme for Vref.
>First - I am not even sure what that means ! and second..theoretically Vef
>carries no current as it
>is the input to a comparator. Its not clear to me why signalling schemes are
>needed for Vref.
>
>Can you clairfy?
>
>Thanks - as always!
>
>Best Regards
>Charles Grasso
>Senior Compliance Engineer
>Echostar Communications Corp.
>Tel: 303-706-5467
>Fax: 303-799-6222
>Cell: 303-204-2974
>Pager/Short Message: 3032042974@xxxxxxxx
>Email: charles.grasso@xxxxxxxxxxxx;
>Email Alternate: chasgrasso@xxxxxxxx
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of steve weir
>Sent: Thursday, July 21, 2005 1:22 PM
>To: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: DDR Vref Bypassing
>
>
>Chris, exactly. IMO, if starvation prevents adequate launch amplitude,
>then the starvation needs to be fixed. Coupling Vref to the image plane is
>about the best that we can do to make single-ended signaling approximate a
>poor man's pseudo differential scheme.
>
>Best regards,
>
>Steve.
>At 11:39 AM 7/21/2005 -0700, Chris Cheng wrote:
> >Anyone who claims he can track highspeed signal power ripple inside the
> >= package with an external resistor/capacitor decoupling combo is =
> >dreaming. Otherwise there will be no such thing as SSO noise. The best
> >you can do is try to hold the reference voltage as close to the =
> >signal reference plane as possible. Majority of packages and PCB use
> >gnd as the continues reference. = Majority of the VTT is AC isolated
> >from the VDDQ which means the signal = return doesn't even completely
> >go back to VDDQ, what exactly is the = "power" you are trying to track
> >? I have done noise margin test that shows decoupling in the wrong
> >place = (like on a memory control package with mixed of output and
> >input ports) = can do more harm than having no decoupling at all.
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx
> >[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bill Wurst
> >Sent: Thursday, July 21, 2005 10:08 AM
> >To: si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: DDR Vref Bypassing
> >
> >
> >Steve,
> >
> >I believe we are perhaps analyzing different physical structures.
> >
> >It seems that the question is whether a single filter capacitor from=20
> >Vref to ground (low pass network) is better than a two capacitor
> >divider =
> >
> >(all pass network with an attenuation factor of 2).
> >
> >Let's start with the Micron DDR2 DIMM spec, which states,
> > "VREF is expected to equal VDDQ/2 of the transmitting device
> > and to track variations in the DC level of the same.
> > Peak-to-peak noise (non-common mode) on VREF may not exceed
> > =B11 percent of the DC value. Peak-to-peak AC noise on VREF may
> > not exceed =B12 percent of VREF (DC). This measurement is to be
> > taken at the nearest VREF bypass capacitor."
> >It also states,
> > "Data timing is now referenced to VREF, provided the
> > DQS slew rate is not less than 1.0V/ns. If the DQS slew rate
> > is less than 1.0V/ns, then data timing is now referenced to
> > VIH(AC) for a rising DQS and VIL(DC) for a falling DQS."
> >
> >Either configuration (low-pass or all-pass) can be made to work. A=20
> >resistor/capacitor (x2y) divider at the transmitting device
> >(all-pass),=20 carried on a trace along with the data to the Vref pins
> >of the receiving =
> >
> >device can give slightly better timing margins (up to 18ps at the
> >worst=20 case of 2% pk-pk noise and 1V/ns slew rate) as follows. The
> >1% matching =
> >
> >of the x2y capacitor will keep non-common mode noise to less than
> >0.5%=20 of the dc value. As you previously stated, copious decoupling
> >of=20 Vdd/Vss is required to keep pk-pk ac noise within 2%, and this
> >amount of =
> >
> >decoupling is perhaps twice better than minimum good design
> >practice.=20 In this way, both the data and Vref signals experience
> >almost identical=20 Vdd/Vss noise all the way to the receiving device.
> >The cancellation is=20 not perfect because a logic '1' only experiences
> >Vdd noise while a logic =
> >
> >'0' only experiences Vss noise; each is attenuated by roughly a
> >factor=20 of two due to both end terminations. Vref is the difference
> >of Vdd and=20 Vss, divided by two, so the two approximately cancel if,
> >and only if,=20 the noise on each rail is approximately equal and
> >in-phase. If the=20 noise is unequal or out-of-phase, then the
> >cancellation is partial, or=20 worse. But is it worse than the
> >low-pass scheme, which takes an average =
> >
> >of all situations? I believe to answer this question will require=20
> >detailed simulation of memory, PCB, controller, and PDS.
> >
> >Unfortunately, there is application literature out there suggesting
> >both =
> >
> >techniques. Which is better - perhaps we are trying to split hairs.
> >
> >Regards,
> >
> > -Bill
> >
> >
> > /************************************
> > / billw@xxxxxxxxxxx /
> > / /
> > / Advanced Electronic Concepts, LLC /
> > / www.aec-lab.com /
> > ************************************
> >=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3
> >D=3D=
> >=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>=
> >=3D=3D=3D=3D=3D=3D=3D=3D=3D
> >steve weir wrote:
> > > At 09:01 PM 7/19/2005 -0400, Bill Wurst wrote:
> > >=20
> > >>Steve,
> > >>
> > >>I'll try to answer your comments/questions as I understand them (see
> > >>response below).
> > >>
> > >>Regards,
> > >>
> > >> -Bill
> > >>
> > >>
> > >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3
> > >>D=3D=
> >=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > >>steve weir wrote:
> > >>
> > >>>Bill, I really question where this assumption of average between
> > >>>Vdd =
> >and
> > >>>Gnd comes from. The noise level on Vdd at the transmitter is not =
> >going to
> > >>>be the same as the instantaneous noise at the receiver, so I don't
> > >>>=
> >buy an
> > >>>argument based on the launch. That leaves us with the transmission
> > >>>channel. What percentage of what couples onto the transmitted
> > >>>signal depends on how the board is constructed.
> > >>
> > >>If the noise on Vdd and Vss at the transmitter propagate to the =
> >receiver
> > >>with the same velocity as the signal, then the noise at both the
> > >>transmitter and receiver will be the same but delayed by the flight
> > >>time.
> > >=20
> > >=20
> > > But I think it doesn't. If I have decent power bypass, then the =
> >radial=20
> > > disturbance on the planes encounters bypass for the transmitter
> > > first, =
> >
> > > where most is supposed to reflect, ( or else we don't have a very
> > > good =
> >
> > > bypass network ), and a little moves on outward, including onward =
> >towards=20
> > > the receiver. When that wave hits the receiver's bypass network, it
> > > =
> >again=20
> > > reflects, and if we have done a job well, very little is left to get
> > > =
> >to the=20
> > > receiver. Conversely, the bypass network near the receiver
> > > localizes =
> >the=20
> > > receiver's current noise.
> > >=20
> > > So, I conclude that by coupling Vdd into Vref I conclude we are =
> >getting:
> > >=20
> > > Vref_ac =3D vector sum ( Vnoise_vss_rec * K1 + Vnoise_vdd_rec * K2
> > >+=20 Vnoise_vss_tx * K3 + Vnoise_vdd_tx * K4 ) =20
> > > Now, I subtract that from my signal that is:
> > >=20
> > > Vsig_ac =3D vector sum ( Vterm * K5 +/- ( Vdd_tx - Vss_tx ) * K6 +=20
> > > Vcavity_ac * K7 )
> > >=20
> > > Since K6 is ideally close to 1.0, K3 and K4 are ideally << 1, and K1 =
> >and=20
> > > K2 are close to 0.5, I see essentially no cancellation of the (
> > > Vdd_tx =
> >+=20
> > > Vss_tx )/2, and injection of a lot of Vnoise_vdd_rec.
> > >=20
> > > Where have I gone wrong?
> > >=20
> > >=20
> > >>Granted, the construction of the board can and will impact this
> > >>assumption. The premise is to make the noise common to both sides
> > >>of the differential receiver, so that the receiver will reject the
> > >>noise =
> >by
> > >>virtue of its CMRR.
> > >=20
> > >=20
> > > Agreed on premise, disagree mightily on implementation.
> > >=20
> > >=20
> > >=20
> > >>At launch, a logic '1' will replicate Vdd noise
> > >>which will be attenuated by terminations at both ends and also
> > >>influenced by any noise on the reference planes as it travels to the
> > >>receiver. Similarly, a logic '0' will replicate Vss noise. Trying
> > >>to make Vref equal to 50% of the difference between the two rails is
> > >>admittedly a compromise and, as you point out, other factors will =
> >reduce
> > >>the cancellation further. Yet I fail to see a better alternative.
> > >=20
> > >=20
> > > Please see above.
> > >=20
> > >=20
> > >>>A split filter is in essence a 2Y common mode filter turned inside
> > >>>out. Impedance mismatch gives rise to mode conversion.which throws
> > >>>=
> >off
> > >>>that 50% divider assumption for equal value ( data sheet )
> > >>>capacitors. This is why we see 2Y RFI filters with a much bigger X
> > >>>capacitor shunting the two lines together- to swamp out the mode
> > >>>conversion. In the Vref application, the X capacitor is
> > >>>represented =
> >by=20
> > >>
> > >>the
> > >>
> > >>>bypass network from Vcc to Vss. That is really ugly, because it =
> >basically
> > >>>says that we need to bypass the heck out of Vdd to get around mode
> > >>>conversion in the Vref bypass caps.
> > >>
> > >>I agree. This is essentially a 2Y CM filter, and Vdd must be
> > >>bypassed to the greatest extent practical.
> > >>
> > >>>The two capacitors in an X2Y match so well that even for analog
> > >>>instrumentation they do not need an X capacitor. I have an =
> >application
> > >>>note on this in ADI's instrumentation amplifier designer's guide, =
> >based on
> > >>>real circuit measurements. An X2Y configured as: Terminal A =3D>
> > >>>=
> >Vdd,
> > >>>Terminal B =3D> Vss, Terminals G1, and G2 =3D> Vref matches to =
> >better than
> > >>>1%. So, if one is bent on implementing the divider, X2Y capacitors
> > >>>=
> >do the
> > >>>job in a way that is basically impossible using separate capacitors
> > >>>=
> >to=20
> > >>
> > >>each
> > >>
> > >>>rail.
> > >>
> > >>Again, I agree. I hedged in my response because I was unsure of the
> > >>matching that could be achieved with x2y capacitors.
> > >>
> > >>>If someone is really bent on this divider approach, then X2Y is =
> >definitely
> > >>>the way to go. But given that people have been building with it,
> > >>>and apparently it has "worked" despite the mode conversion with
> > >>>regular=20
> > >>
> > >>caps, I
> > >>
> > >>>really question the validity of the approach in the first place.
> > >>>Do =
> >you
> > >>>know what the physical basis for the rationale of the divider is =
> >supposed
> > >>>to be?
> > >>
> > >>Hopefully, unless I've missed something, I've answered this in my
> > >>response to the first paragraph. Please let me know if I haven't.
> > >>
> > >>>Regards,
> > >>>
> > >>>
> > >>>Steve.
> > >>>
> > >>>At 12:48 PM 7/19/2005 -0400, Bill Wurst wrote:
> > >>>
> > >>>
> > >>>>Chris,
> > >>>>
> > >>>>The answer to your question lies in understanding the function of
> > >>>>=
> >the
> > >>>>Vref line. DDR, as well as DDR2, utilize differential receivers
> > >>>>to process single-ended inputs that have been generated by drivers
> > >>>>=
> >which
> > >>>>swing in a balanced fashion around the mid-point of the VDD/GND =
> >system.
> > >>>> To properly process these single-ended inputs, the inverting
> > >>>> input =
> >of
> > >>>>each differential receiver is connected to Vref. The receivers
> > >>>>will work best when Vref equals exactly 0.5*(VDD-GND), including
> > >>>>any =
> >noise
> > >>>>that is present on the VDD/GND system. The purpose of placing an
> > >>>>=
> >equal
> > >>>>amount of capacitance from Vref to VDD and from Vref to GND is to
> > >>>>=
> >form
> > >>>>an ac divider that keeps Vref equal to 0.5*(VDD-GND) over all
> > >>>>frequencies. The capacitance should be large enough to swamp out
> > >>>>=
> >any
> > >>>>parasitic capacitance that exists which could imbalance Vref.
> > >>>>
> > >>>>I'll have to hedge on the second question which was "whether an
> > >>>>x2y capacitor is better than two discrete capacitors" since I
> > >>>>don't know enough about x2y devices. Properly configured, an x2y
> > >>>>capacitor =
> >could
> > >>>>perform better, but the bottom line comes down to the accuracy of
> > >>>>=
> >the ac
> > >>>>divider.
> > >>>>
> > >>>>Regards,
> > >>>>
> > >>>> -Bill
> > >>>>
> > >>>>
> > >>>> /************************************
> > >>>> / billw@xxxxxxxxxxx /
> > >>>> / /
> > >>>> / Advanced Electronic Concepts, LLC /
> > >>>> / www.aec-lab.com /
> > >>>> ************************************
> > >>>>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > >>>>=3D=
> >=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3
> >D=3D=
> >=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > >>>>Christopher R. Johnson wrote:
> > >>>>
> > >>>>
> > >>>>>I have seen references that have Vref bypass capacitors to both
> > >>>>>=
> >VDD and
> > >>>>>GND. Other references have capacitors only to GND. Is it really
> > >>>>>necessary to have "balanced" capacitors on the Vref lines? Why?
> > >>>>>=
> >If the
> > >>>>>"balanced" design is desirable, would an X2Y capacitor be a good
> > >>>>>=
> >choice,
> > >>>>>since it is "2 capacitors in one"?
> > >>>>>
> > >>>>>Regards,
> > >>>>>
> > >>>>>Chris Johnson
> > >>>>>-----------------------------------------------------------------
> > >>>>>-
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