[SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff

Putting it in a more every-day language, I
would call it "fake differential" which may
sound less undesirable...

Arpad
-------------------------------------------

-----Original Message-----
From: Christopher.Jakubiec@xxxxxxxxxxxx =
[mailto:Christopher.Jakubiec@xxxxxxxxxxxx]=20
Sent: Friday, July 22, 2005 11:46 AM
To: Muranyi, Arpad; Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo =
diff

"pseudo" is defined in the dictionary as false or deceptive.......I
don't know about you but I don't want want signaling scheme to be
either! :)

-Chris


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Muranyi, Arpad
Sent: Friday, July 22, 2005 2:29 PM
To: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff


Chris,

I don't think I am confused, I think we have a serious terminology
difference as far as "pseudo" is concerned and thereby a communication
problem.  It looks like that the word "pseudo" can be used in many
different ways...

You seem to be talking mostly about how many signal traces
go to the receivers, and I was mostly talking about driver
architectures, assuming that the signal is always carried by two signal
traces to the receiver.

And I never mentioned "current mode driver for DDR".

Arpad
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
=3D3D=3D
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3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
=3D3D=3D
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
=3D On Behalf Of Chris Cheng
Sent: Friday, July 22, 2005 11:08 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff

I think you are confused.=3D20
Both differential and pseudo differential signaling scheme use truely =
=3D
differential receivers. The only difference is differential scheme =3D
provide a regular output and the complement of the output to feed into =
=3D
both sides of the differential receiver while pseudo differential scheme
=3D only send out the regular output and tie the other input of the =3D
differential receiver to a known reference voltage, typically the =3D
mid-point between Voh/Vhl. There is no such thing as current mode driver
for DDR. The original intend of the pseudo differential receiver (such
as the =3D original GTL system) was to track low speed VTT differences
across =3D vastly seperated boards in a backplane system while saving =
pins
and I/O =3D by not providing the complement output. It makes the
assumption that the =3D combined reference plane (gnd in most cases) and
Vref generation through =3D the resistor divider is sufficient to hold =
the
common mode variation in =3D check. ________________________________

From: si-list-bounce@xxxxxxxxxxxxx on behalf of Muranyi, Arpad
Sent: Fri 7/22/2005 9:34 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff



Charles,=3D3D20

By pseudo differential we mean that you associate two
normal single ended buffers and/or receivers and call
them differential because the signal you driver through
them are complementary.

The problem with this scheme is that each of the two
signals will be ground and/or power supply referenced,
and as such, the noise in any of the power supplies will
go right into your signals.  This is what the Vref comment
was referring to.

A fully differential system would be completely
independent from the rails, floating anywhere it
pleases, yet still have a well defined differential
voltage between the pair.  In a driver design this
can be achieved with four current steering transistors surrounded by two
current sources, one on the gnd rail side and the other on the power
rail side of the switchers.  The two current sources are responsible for
letting the switchers float and be independent from the rails.

A "compromise" solution is half way between these two,
hence I like to call it "half differential", where
one current source and two of the switchers are replaced
by a couple of resistors.  Several well known buses use
this configuration (SATA, PCIexpress, USB).  In these
designs the "differential signal" is still referenced
to one of the supplies because of the presence of the resistors, but it
is independent from the other rail, because there is still one current
source on the other side.  For these designs you have to keep one of the
rails very clean (the one to which the resistors are connected), because
the noise in that rail will still go into your signal as common mode
noise.

These considerations also have an impact on how you
reference your transmission lines, and how you terminate
them (common mode, differential mode, pi termination,
etc...), power delivery noise, etc...  However, I will
leave these subjects alone for now.

I hope this will help your understanding of differential signaling.

Arpad Muranyi
Intel Corporation
=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D=
3D3D=3D3D3D=3D3D3D=3D3D3D=3D3
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3D
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3D
=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D





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