[SI-LIST] Re: DDR Vref Bypassing
- From: Dagmara Avanindra <dagmara.avanindra@xxxxxxxxx>
- To: Charles.Grasso@xxxxxxxxxxxx
- Date: Mon, 18 Jul 2005 15:58:27 -0700
Well, actually it depends on the boards stack-up.=20
If your VCC plane is coupled to GND plane with thin dielectric -
around 2 mils, the noise on that plane is very hard to distinguish
from the noise on the adjacent GND plane.
Regards,=20
Dagmara Avanindra
On 7/18/05, Grasso, Charles <Charles.Grasso@xxxxxxxxxxxx> wrote:
> Be very careful with the decoupler to Vcc. You *will*
> couple power noise onto Vref that only has a 50mV limit.
>=20
> Best Regards
> Charles Grasso
> Senior Compliance Engineer
> Echostar Communications Corp.
> Tel: 303-706-5467
> Fax: 303-799-6222
> Cell: 303-204-2974
> Pager/Short Message: 3032042974@xxxxxxxx
> Email: charles.grasso@xxxxxxxxxxxx;
> Email Alternate: chasgrasso@xxxxxxxx
>=20
>=20
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
> Behalf Of Tom Dagostino
> Sent: Monday, July 18, 2005 1:38 PM
> To: Dale L. Sanders; crjohnson11@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR Vref Bypassing
>=20
>=20
> Dale
>=20
> I read the initial post as saying connect a capacitor from Vref to ground
> and another capacitor from Vref to Vcc. Your circuit, if I understand it
> correctly, is to connect one half of your X2Y cap from Vref to ground and
> the other half from Vcc to ground. This is not apples apples but apples =
and
> oranges I believe.
>=20
> Tom Dagostino
> Teraspeed(R) Labs
> 13610 SW Harness Lane
> Beaverton, OR 97008
> 503-430-1065
> tom@xxxxxxxxxxxxx
> www.teraspeed.com
>=20
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> 401-284-1827
>=20
> -----Original Message-----
> From: Dale L. Sanders [mailto:Dale@xxxxxxx]
> Sent: Monday, July 18, 2005 11:47 AM
> To: tom@xxxxxxxxxxxxx; crjohnson11@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: DDR Vref Bypassing
>=20
>=20
> Tom,
> I agree that standard capacitors that could be an issue of coupling noise
> between VDD and Vref.
>=20
> But if balance is critical, X2Y can be attached in a "Circuit 1"
> configuration ... where "A" terminal is attached to VDD and 'B' terminal =
is
> attached to Vref and 'G1' and 'G2' are attached to GND. X2Y would only ha=
ve
> minimal noise coupling between VDD and Vref.
>=20
> To illustrate this, you can see the data presented at the Freescale
> Technology Forum Workshop last month (June) in Orlando, FL (pages 49 - 52=
).
>=20
> http://www.x2y.com/x2y/x2y.nsf/1/ftfdecouple.pdf/$FILE/ftfdecouple.pdf
>=20
>=20
>=20
> Dale L. Sanders
> Application Engineer
> X2Y Attenuators, LLC
>=20
>=20
>=20
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
> Behalf Of Tom Dagostino
> Sent: Monday, July 18, 2005 1:16 PM
> To: crjohnson11@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR Vref Bypassing
>=20
> Using capacitors to both ground and Vcc seems to be an invitation to
> disaster. The idea of putting a cap to a reference voltage is to keep the=
AC
> impedance low and reference voltage referenced to ground (usually). Most
> supplies have a lot of noise on them when measured to ground. Adding a c=
ap
> from the supply to the reference voltage will inject this unwanted noise
> into Vref. If your circuit is set up such that its reference is Vcc then=
a
> cap to Vcc would be good and a cap to ground would inject noise.
>=20
> Tom Dagostino
> Teraspeed(R) Labs
> 13610 SW Harness Lane
> Beaverton, OR 97008
> 503-430-1065
> tom@xxxxxxxxxxxxx
> www.teraspeed.com
>=20
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> 401-284-1827
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]O=
n
> Behalf Of Christopher R. Johnson
> Sent: Monday, July 18, 2005 10:49 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR Vref Bypassing
>=20
>=20
> I have seen references that have Vref bypass capacitors to both VDD and
> GND. Other references have capacitors only to GND. Is it really
> necessary to have "balanced" capacitors on the Vref lines? Why? If the
> "balanced" design is desirable, would an X2Y capacitor be a good choice,
> since it is "2 capacitors in one"?
>=20
> Regards,
>=20
> Chris Johnson
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