[SI-LIST] Re: DDR Vref Bypassing

A word of caution regarding the use of a unity gain op-amp to buffer the
reference voltage.
It typically works well for DC, but don't forget to consider what
bandwidth is needed to effectively handle dynamic load changes.


Best Regards=20
Juergen Flamm
 =20
 =20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Mahabala Shetty
Sent: Wednesday, July 20, 2005 7:26 PM
To: weirsi@xxxxxxxxxx; Charles.Grasso@xxxxxxxxxxxx;
sunil.mekad@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: billw@xxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Vref Bypassing

=20
Hi Sunil,=20

Use an unity gain buffer(op-amp) for each of the Vref so you could avoid
noise.=20

Rgds,=20

Mahabala.




>From: steve weir <weirsi@xxxxxxxxxx>
>Reply-To: weirsi@xxxxxxxxxx
>To: Charles.Grasso@xxxxxxxxxxxx,"'sunil.mekad@xxxxxxxxx'"
<sunil.mekad@xxxxxxxxx>,"'si-list@xxxxxxxxxxxxx'"
<si-list@xxxxxxxxxxxxx>
>CC: "'billw@xxxxxxxxxxx'" <billw@xxxxxxxxxxx>
>Subject: [SI-LIST] Re: DDR Vref Bypassing
>Date: Wed, 20 Jul 2005 13:21:26 -0700
>
>Phase! Phase! Phase!
>At 10:14 AM 7/20/2005 -0600, Grasso, Charles wrote:
>>One way is to generate Verve from a separate switcher that tracks the=20
>>DVD ripple. Kind of expensive though!
>>
>>Best Regards
>>Charles Grasso
>>Senior Compliance Engineer
>>Echostar Communications Corp.
>>Tel:  303-706-5467
>>Fax: 303-799-6222
>>Cell: 303-204-2974
>>Pager/Short Message:  3032042974@xxxxxxxx
>>Email: charles.grasso@xxxxxxxxxxxx;
>>Email Alternate: chasgrasso@xxxxxxxx
>>
>>
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx=20
>>[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
>>Behalf Of sunil.mekad@xxxxxxxxx
>>Sent: Tuesday, July 19, 2005 10:06 PM
>>To: si-list@xxxxxxxxxxxxx
>>Cc: billw@xxxxxxxxxxx
>>Subject: [SI-LIST] Re: DDR Vref Bypassing
>>
>>
>>
>>=3D0D
>>Team,
>>
>>I have a question here in similar lines to the DDR2 vref. I am trying=20
>>to generate the Vref through a resistor divider approach for the=20
>>QDR-II and
>>Virtex-4 FPGA (that acts as controller). On board I have 3 such=20
>>interfaces (i.e 3 QDR to FPGA single clock mode connection).
>>
>>I am generating the 0.75V from the 1.5V VDDQ by a resistor divider=20
>>using
22
>>ohm, 0.1% tol. The devider network is decoupled with  0.01uF caps and
2.2uF
>>caps (X7R) to ground.
>>
>>I am feeding a single such divider network to the 3 FPGA vref inputs
(total
>>of 18 Vref i/ps). And independent such divider network for each QDR-II

>>Srams. (Since the QDR-II SRAM have more HSTL I/P pins than FPGA=20
>>controller)=3D0D
>>
>>How do I make my design foolproof so that the ripple in Vref can be
avoided
>>due to static and AC current requirements? Do I need to split these
resistor
>>divider to each FPGA just to be sure that the combined AC/Static=20
>>current does not dip my Vref to below desireable levels?
>>
>>Thanks
>>Sunil
>>
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx=20
>>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>>On Behalf Of Bill Wurst
>>Sent: Wednesday, July 20, 2005 6:32 AM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: DDR Vref Bypassing
>>
>>Steve,
>>
>>I'll try to answer your comments/questions as I understand them (see=20
>>response below).
>>
>>Regards,
>>
>>      -Bill
>>
>>
>>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
>>3D=3D3D
=3D
>>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
>>steve weir wrote:
>>>Bill, I really question where this assumption of average between=20
>>>Vdd=3D0D and Gnd comes from.  The noise level on Vdd at the =
transmitter

>>>is not=3D0D going to be the same as the instantaneous noise at the=20
>>>receiver, so I=3D0D don't buy an argument based on the launch.  That=20
>>>leaves us with the=3D0D transmission channel.  What percentage of =
what=20
>>>couples onto the=3D0D transmitted signal depends on how the board is=20
>>>constructed.
>>If the noise on Vdd and Vss at the transmitter propagate to the=20
>>receiver with the same velocity as the signal, then the noise at both=20
>>the
transmitter
>>and receiver will be the same but delayed by the flight time. =20
>>Granted,
the
>>construction of the board can and will impact this assumption.  The
premise
>>is to make the noise common to both sides of the differential=20
>>receiver, so that the receiver will reject the noise by virtue of its=20
>>CMRR.  At launch,
a
>>logic '1' will replicate Vdd noise which will be attenuated by
terminations
>>at both ends and also influenced by any noise on the reference planes=20
>>as
it
>>travels to the receiver.  Similarly, a logic '0' will replicate Vss
noise.
>>Trying to make Vref equal to 50% of the difference between the two=20
>>rails
is
>>admittedly a compromise and, as you point out, other factors will=20
>>reduce
the
>>cancellation further.  Yet I fail to see a better alternative.
>>>=3D0D
>>>A split filter is in essence a 2Y common mode filter turned =
inside=3D0D

>>>out.  Impedance mismatch gives rise to mode conversion.which=20
>>>throws=3D0D off that 50% divider assumption for equal value ( data=20
>>>sheet )=3D0D capacitors.  This is why we see 2Y RFI filters with a =
much

>>>bigger X=3D0D capacitor shunting the two lines together- to swamp out =

>>>the mode=3D0D conversion.  In the Vref application, the X capacitor =
is=20
>>>represented=3D0D by the bypass network from Vcc to Vss.  That is =
really

>>>ugly, because=3D0D it basically says that we need to bypass the heck=20
>>>out of Vdd to get=3D0D around mode conversion in the Vref bypass =
caps.
>>I agree.  This is essentially a 2Y CM filter, and Vdd must be bypassed

>>to the greatest extent practical.
>>>=3D0D
>>>The two capacitors in an X2Y match so well that even for analog=3D0D=20
>>>instrumentation they do not need an X capacitor.  I have an=3D0D=20
>>>application note on this in ADI's instrumentation amplifier=20
>>>designer's
>>
>>>guide, based on real circuit measurements.  An X2Y configured as: =
=3D0D

>>>Terminal A =3D3D> Vdd, Terminal B =3D3D> Vss, Terminals G1, and G2 =
=3D3D>=20
>>>Vref =3D
>>=3D0D
>>>matches to better than 1%.  So, if one is bent on implementing =
the=3D0D

>>>divider, X2Y capacitors do the job in a way that is basically=3D0D=20
>>>impossible using separate capacitors to each rail.
>>Again, I agree.  I hedged in my response because I was unsure of the=20
>>matching that could be achieved with x2y capacitors.
>>>=3D0D
>>>If someone is really bent on this divider approach, then X2Y is=3D0D=20
>>>definitely the way to go.  But given that people have been=20
>>>building=3D0D with it, and apparently it has "worked" despite the =
mode=20
>>>conversion=3D0D with regular caps, I really question the validity of=20
>>>the approach in=3D0D the first place.  Do you know what the physical=20
>>>basis for the=3D0D rationale of the divider is supposed to be?
>>Hopefully, unless I've missed something, I've answered this in my=20
>>response to the first paragraph.  Please let me know if I haven't.
>>>=3D0D
>>>Regards,
>>>=3D0D
>>>=3D0D
>>>Steve.
>>>=3D0D
>>>At 12:48 PM 7/19/2005 -0400, Bill Wurst wrote:
>>>=3D0D
>>>>Chris,
>>>>
>>>>The answer to your question lies in understanding the function of=20
>>>>the=3D0D Vref line.  DDR, as well as DDR2, utilize differential=20
>>>>receivers to=3D0D process single-ended inputs that have been =
generated

>>>>by drivers which=3D0D swing in a balanced fashion around the =
mid-point

>>>>of the VDD/GND
>>system.
>>>>  To properly process these single-ended inputs, the inverting=20
>>>>input=3D0D of each differential receiver is connected to Vref.  The=20
>>>>receivers=3D0D will work best when Vref equals exactly =
0.5*(VDD-GND),=20
>>>>including any=3D0D noise that is present on the VDD/GND system.  The =

>>>>purpose of placing=3D0D an equal amount of capacitance from Vref to=20
>>>>VDD and from Vref to GND=3D0D is to form an ac divider that keeps =
Vref

>>>>equal to 0.5*(VDD-GND) over=3D0D all frequencies.  The capacitance=20
>>>>should be large enough to swamp out=3D0D any parasitic capacitance=20
>>>>that exists which could imbalance Vref.
>>>>
>>>>I'll have to hedge on the second question which was "whether an=20
>>>>x2y=3D0D capacitor is better than two discrete capacitors" since I=20
>>>>don't know=3D0D enough about x2y devices.  Properly configured, an =
x2y

>>>>capacitor could
>>
>>>>perform better, but the bottom line comes down to the accuracy of=20
>>>>the=3D0D ac divider.
>>>>
>>>>Regards,
>>>>
>>>>     -Bill
>>>>
>>>>
>>>>       /************************************
>>>>      /         billw@xxxxxxxxxxx         /
>>>>     /                                   /
>>>>    / Advanced Electronic Concepts, LLC /
>>>>   /           www.aec-lab.com         /
>>>>   ************************************
>>>>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3=
D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3
>>>>D=3D
>>>>3D=3D
>>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
>>3D=3D3D
=3D
>>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D
>>>>Christopher R. Johnson wrote:
>>>>
>>>>>I have seen references that have Vref  bypass capacitors to both=20
>>>>>VDD
>>and
>>>>>GND.  Other references have capacitors only to GND.   Is it really
>>>>>necessary to have "balanced" capacitors on the Vref lines?  Why?
>>>>>If=3D0D the "balanced" design is desirable, would an X2Y capacitor =
be

>>>>>a good=3D0D choice, since it is "2 capacitors in one"?
>>>>>
>>>>>Regards,
>>>>>
>>>>>Chris Johnson
>>>>>------------------------------------------------------------------
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