[SI-LIST] Re: DDR Interface Topology
- From: "Todd Westerhoff" <twesterh@xxxxxxxxxx>
- To: <kalevi@xxxxxxxxxx>, <arjun.bingipur@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 7 Nov 2006 14:29:15 -0500
All,
It's worth noting that SI analyses must cover the different operating corner
(min/typ/max) conditions under which the interface must operate. If you're
using IBIS models provided by the semiconductor vendor, then the
combinations of process / voltage / temperature that represent min/typ/max
conditions have been preset in the IBIS model.
Don't forget that device timing may change by corner case as well, and
you'll have to combine the correct combinations of device timing and SI
analyses when determining system timing margins.
Todd.
Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@xxxxxxxxxx
www.sisoft.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Kai Keskinen
Sent: Monday, November 06, 2006 7:06 PM
To: arjun.bingipur@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Interface Topology
Arjun:
I'm pretty sure that if you are using some kind of IP firmware for your
FPGA, it will give you fairly detailed timing numbers. If you are writing
your own code, you can come up with timing numbers that work. You start from
the DDR SDRAM data sheet timing numbers and the memory controller numbers
and do a static timing analysis. You then simulate one net of each type at
the distance you are placing the memories to get a pretty good estimate of
switching times. You then put those numbers back in your timing spread
sheets and adjust track length and/or placement until you have centered set
up and hold times for all classes of signals (data, address/control,
strobes, masks). There is no magic answer. With a programmable device, you
have a lot more freedom than with a controller from a CPU or other big asic.
You have to do some math and research. Don't forget to do a post-route check
to make sure every pin pair works. Sometimes things get moved during layout
even when you thought they were fixed.
Enjoy,
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bingipur, Arjun
Sent: Saturday, November 04, 2006 2:53 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR Interface Topology
Hi,
We are designing a FPGA based system with four DDRs interfacing
independently with the FPGA. Here, all the address, data and control
signals are point-to-point. I can see that Balanced T Routing topology
is preferred where in the data and strobe signals are point-to-point and
address/control is point-to-four-point. I'm curious to know if there is
preferred routing topology and length matching schemes where in all the
DDRs interface independently with the FPGA with its own address, data
and control signals. Or, is it just that I'll have to make sure the
lengths are matched for each data group and across the entire channel.
Regards,
Arjun Bingipur
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