[SI-LIST] Cycle time requirement for control signal in MODE PCIX cells

Refered PCI-SIG document : PCI-X Electrical and
Mechanical Addendum to the
PCI Local Bus Specification
Revision 2.0a
August 22, 2003

I am working on a PCIX-MODE2 library.
Is there any cycle time requirement for outpur enable or termination
enable signal in a PCIX-MODE2 cell ?

The frequency requirement for data level shifter is 266Mhz.
But what frequency of operation other level shifter(output enable/
termination enable) should expect ?


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