[SI-LIST] Re: Current mode current stealing simulation by IBIS file
- From: "Sogo Hsu" <sogo.hsu@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 01 Mar 2004 10:53:48 -0000
[Sorry, resend]
Hi, Arpad,
Thank you for your fruitful comments. Current mode current stealing
is widely employed in clock gen. technology for Intel, such as
CK409, CK410 etc.. We performed the simulation works by using
SPECCTRAQuest and Hspice as well. The models are all in IBIS file
format in v3.2. These two famous simulation tools presented almost
the same results. The most interesting is the discrepancy
qualitatively between simulation and measurement and/or prediction
theoretically. Theoretically, the parallel termination resistors
shall be placed close to the driver as possible for current mode
current stealing technology and close to the end of receiver for
voltage mode to eliminate the reflection. However, the simulation
results did not indicate this trend for current mode current
stealing buffer. That is said, we also need to place the termination
resistor close to the end of receiver to get good signal integrity.
Obviously, this is not meeting the trend of measurement and
theoretical prediction. As I said in the previous message, this
trend can be exactly predicted if we create an equivalent buffer
model in spice format. We are unable to ensure the root cause of
this discrepancy. It may be the limitation of IBIS v3.2 as Lynne
said, or the solver=A1=A6s issue. For us, we can only get the model
from chip vendor. We hope we can make some modifications on IBIS
files and/or simulation set-up to obtain accurate simulation results
on this issue. Thanks for any Guru can share his/her experience.
Best Regards,
Sogo Hsu, Ph. D.
Simulation center/PCEG/Foxconn Electronic
--- In si-list@xxxxxxxxxxxxxxx, "Muranyi, Arpad"
<arpad.muranyi@xxxx> wrote:
> Sogo,
>
> I am not sure what "current mode current stealing" is, but
> to respond to the rest of your question I would like to say
> that there must be another reason that makes your IBIS
> simulation different from SPICE or measured.
>
> In terms of the IV curve of a device or its simulation there
> is really no such thing as current or voltage mode. The shape
> of the IV curve determines it all. If your IV curve is a
> horizontal line, you have an ideal current source. If your
> IV curve is a vertical line, you have an ideal voltage source.
> If your IV curve is a diagonal line of some slope, you have
> a linear resistor, and finally if you have a curved IV curve
> you have a (non linear) diode, transistor or some sort of a
> device. There are no ifs and buts about this. You tool may
> select current as a known and voltage as the unknown, or vice
> versa, but the model is still the same IV curve.
>
> If there are discrepancies between your SPICE and IBIS models
> that means that either the IV curves are not the same, or there
> are perhaps other elements (or behaviors) in the SPICE model
> which are not described by the IV and Vt curves of your IBIS
> model. If there are features in the buffer which are fancy
> (dynamic) effects that IBIS 3.2 cannot describe with its
> relatively simple IV and Vt curve approach, you may need
> to resort to *-AMS as your modeling language as Lynne
> suggested. But this would not fall into the definition
> of "current mode" vs. "voltage mode".
>
> I hope this helps,
>
> Arpad Muranyi
> Intel Corporation
>
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
=3D3D=3D3D=3D
>
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
=3D3D=3D3D=3D
> =3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
>
>
> -----Original Message-----
> From: si-list-bounce@xxxx
> [mailto:si-list-bounce@xxxx]On Behalf Of Sogo Hsu
> Sent: Wednesday, February 25, 2004 12:11 AM
> To: si-list@xxxx
> Subject: [SI-LIST] Current mode current stealing simulation by
IBIS file
>
>
> Hi, Gurus,
>
> A question regarding current mode current stealing circuit=3D20
> simulation confused me for a long time. The simulation results=3D20
> totally different from the measured as well. To understand the
cause=3D20
> of discrepancy, I tried to set up two kinds of circuit, one is=3D20
> voltage mode and the other one is current mode. In general, IBIS=3D20
> file describe the v/t curves of I/O cell with test feature. We
can=3D20
> easily generate the same v/t curve for these two. However, the
Spice=3D20
> simulation indicated the results are totally different if the
whole=3D20
> link is under considered. The behavior of current mode spice
model=3D20
> is similar with the measured. In my opinion, this phenomenon can
be=3D20
> analog to TE and TM mode. Therefore, the refection condition is=3D20
> definitely different even they have owned same v/t curve in IBIS=3D20
> file. My question is, how we overcome this issue if we only use
IBIS=3D20
> file for simulation. In general, we can only get IBIS files from=3D20
> vendors.=3D20
> Can any expert on this topic share the experience to me? Thank
you=3D20
> in advance.
>
> Best regards,
>
> Sogo Hsu, Ph. D.
> Simulation center/PCEG/Foxconn Electronic
>
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