Thought I'd throw in my 2 cents... From my experience, there are 4 issues (at least) we are trying to address with ground stitching vias, and they are very similar to the issues involved in providing enough nearby ground pins on connectors and packages. =20 The first, maintaining impedance, is relatively straightforward and reproducible in 3-D simulations (though not easily - you must consider the effect of your boundary carefully, and it's only applicable to the specific stackup/geometries modeled). To my simplistic thinking, it's mostly related to the distance between the signal and the nearest ground via. A ground via nearby reduces the loop inductance and simultaneously increases capacitance between the signal and ground, reducing the impedance. The tricky part, in my opinion, is that this may or may not be a good thing. If you are going through a board with a THICK core (4-layer, 62mil), such that the via tends to appear inductive, relative to the ciruit's nominal impedance (usually about 50 ohms), the nearby ground via can be a good thing. If you are going through a board with LOTS of plances very close together such that the via appears capacitive, the further reduction in impedance due to the nearby ground via can make a situation worse. This is true for both single-ended and differential vias, though differential vias tend to have a lower-than-optimal impedance, in my experience. Only 3-D modeling and/or measurement of test boards with your exact stackup/dimensions can say what the preferred choice is to maintain proper impedance. For a 133MHz bus, I doubt this will be a substantial factor (though I can envision a signal via in the middle of a LARGE area without any ground vias possibly being affected). The second, reducing crosstalk due to several signals being forced to use the same inductive ground path, is less straightforward to model and/or measure (the model/measurement of the signal path must comprehend the impact on the return path of nearby aggressors). I haven't seen any extensive work on this published for vias, though there should be quite a bit available on the similar problem with connectors. Most future high-speed designs go to differential signaling, which reduces the problem (as it does for connectors, another plus for diff. signaling). As others have alluded to, this could be troublesome for your design. I'd look carefully to ensure several signals aren't forced to share the same inductive return path. The third issue that folks have raised is related to the first - trying to maintain a nice TEM (or quasi-TEM) wave in the face of the ugly reality of PCB construction, with its multiple planes, layers, and necessary via physical design limitations. I haven't seen any practical way of doing this - I think we're going to have to absorb some ugliness due to vias for a while. Again, we hit this in connectors too (and the interfaces to the connector), though we try to minimize the effects with careful modeling and design. A fourth, more subtle issue for differential signals, is trying to maintain the same odd and even mode impedances as the transmission lines leading into and out of the via (I.E., coupling of the vias is same as that for the traces). The position of the corresponding ground via(s) plays a part here. Fortunately, I don't think we'll have to worry about this for a while - connectors don't pay much attention to it (that I know of), and I haven't seen it highlighted as a problem for a design solution space... Disclaimer: The content of this message is my personal opinion only and although I am an employee of Intel, the statements I make here in no way represent Intel's position on the issue, nor am I authorized to speak on behalf of Intel on this matter. Jeff Loyer ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu