[SI-LIST] Re: Current Return Vias

You make a good point Scott, and an important distinction when doing BGA
pinout development work. Certainly the PDS issues need to be dealt with
properly, i.e. minimizing the power delivery impedance and limiting the
high frequency power deliver demands placed on the package, etc. But
it's also necessary to develop a pinout after thoroughly considering the
system application...thereby following an application specific theme
rather than a generic set of rules to BGA pin assignments. As you
mentioned earlier, if all the signals in your application are ground
referenced in the system planar, and also ground referenced in the
package substrate routing, then ground vias within the signal via field
can be most helpful when addressing the z-axis transition. A good planar
PDS will not solve this issue by itself. Of course the PDS issues should
also be dealt with properly, keeping in mind all the good design
practices published by Teraspeed, Larry and Istvan.

Regards,
Dean Gonzales
Broadcom's ServerWorks   =20
=20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Wednesday, July 26, 2006 11:23 AM
To: Istvan.Novak@xxxxxxx
Cc: perry.qu@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Current Return Vias

Istvan,
I will agree, sort of.  Design for clean power, signal return path
integrity, and emissions are all important design tasks, each affecting
the other.  I like your unified approach.  As you know, Steve and I
think along similar lines.  However, in general usage in the literature,
on the si-list, and in the minds of most readers, PDS generally
encompasses the power delivery aspects of a design from VRM to die,
while excluding the signal paths, which are generally known as SI
related issues.  But, as we know, there are intersections and overlaps
between each of these.

Since most readers treat PDS design as a separate issue from signal path
design, I think it's appropriate to state that a PDS only design
approach to noise reduction may not be enough to solve all problems.=20

regards,

Scott


Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed(r) is the registered service mark of Teraspeed Consulting
Group LLC



Istvan Novak - Board Design Technology wrote:
> Scott,
> I think it depends on what one considers to be a good PDS design.
>
> In my view, the PDS functions are:
>
> - provide clean power to the chips (primary function)
> - provide adequate reference path for signals (optional function)
> - make sure that the radiation is within allowed limits (optional=20
> function)
>
> The second and third functions are optional, because it depends on the

> construction whether those are functions of the PDS that we depend on=20
> or not.  The design target is not necessarily the same along those=20
> three functions: a design, which is good enough to provide=20
> sufficiently clean power to the silicon, may fail in providing good=20
> enough return path or may emit above allowed limits, and vica versa.
>
> Regards,
> istvan
>
>
>
> Scott McMorrow wrote:
>
>  =20
>> Ding, ding, ding ... this is a good example of a design with a poor=20
>> return path due to signal via crowding.  Adding ground vias within=20
>> the signal via field, for a gnd referenced design, will undoubtedly=20
>> help, as long as the ground vias are interspersed within the signal
via field.
>> The PDS will not help you when signal edge rates are in the several=20
>> hundred picosecond range.
>>
>> Those who believe that "good" PDS design will solve all signal via=20
>> related crosstalk problems are woefully mistaken.
>>
>>
>>
>>
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 121 North River Drive
>> Narragansett, RI 02882
>> (401) 284-1827 Business
>> (401) 284-1840 Fax
>>
>> http://www.teraspeed.com
>>
>> Teraspeed(r) is the registered service mark of Teraspeed Consulting=20
>> Group LLC
>>
>>
>>
>> Perry Qu wrote:
>> =20
>>
>>    =20
>>> Interesting topic. We recently had a design with a SDRAM interface=20
>>> consists of 5 SDRAMs, 2 pairs clamshelled and one standalone. It's=20
>>> running on 155 MHz clock single data rate so not a fast interface by

>>> today's standard. For the clamshelled SDRAMs, we measured the=20
>>> address signals and the waveform on the top and bottom sometimes are

>>> quite different, specifically, one of the SDRAM (could be either top

>>> or bottom depending on which address pin we probe) shows very=20
>>> visible crosstalk and worse shelf on edge.  The result is less
margin for timing.
>>>
>>> This can't be caused by topology as we length-matched the trace from

>>> SDRAM pin to the branch via in a mixture of star/far-end cluster=20
>>> topology. The only thing I can think of is return current as most of

>>> the signals vias are under the middle of the SDRAM packaging with no

>>> ground/power via really closeby. The SDRAM packaging is not well=20
>>> done in my opinion as they have most of the power/ground pins on one

>>> half of the chip, and very few reference pins on the other half=20
>>> where all address pins locate. To make it worse,  the routing layer=20
>>> is all over the stackup and it can jump from a layer close to top to

>>> a layer close to bottom and then jump back, with no return vias=20
>>> close to signal vias, although they all reference to GND (we have=20
>>> multiple GND planes throughout the stackup). The worse waveform=20
>>> seems always occurs at the SDRAM with bigger jump in terms of=20
>>> reference planes thus larger return loop area, which is the cause=20
>>> for crosstalk and higher inductance on return and shelf on edge. I
decide to add some ground vias close to the signal vias for our next
design which uses same chips.
>>>
>>> Regards
>>>
>>> Perry
>>>
>>>
>>> =
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>>>
>>> Perry Qu
>>>
>>> Design & Qualification, Alcatel Canada
>>>
>>> 600 March Road, Ottawa ON, K2K 2E6
>>>
>>> DID: 613-7846720  Fax: 613-5993642
>>>
>>> Email: perry.qu@xxxxxxxxxxx
>>>
>>> =
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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>>>
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