[SI-LIST] Re: Current Return Vias
- From: Istvan Novak - Board Design Technology <Istvan.Novak@xxxxxxx>
- To: scott@xxxxxxxxxxxxx
- Date: Wed, 26 Jul 2006 13:43:22 -0400
Scott,
I think it depends on what one considers to be a good PDS design.
In my view, the PDS functions are:
- provide clean power to the chips (primary function)
- provide adequate reference path for signals (optional function)
- make sure that the radiation is within allowed limits (optional function)
The second and third functions are optional, because it depends on the
construction whether those are functions of the PDS that we depend on
or not. The design target is not necessarily the same along those
three functions: a design, which is good enough to provide sufficiently
clean power to the silicon, may fail in providing good enough return
path or may emit above allowed limits, and vica versa.
Regards,
istvan
Scott McMorrow wrote:
>Ding, ding, ding ... this is a good example of a design with a poor
>return path due to signal via crowding. Adding ground vias within the
>signal via field, for a gnd referenced design, will undoubtedly help, as
>long as the ground vias are interspersed within the signal via field.
>The PDS will not help you when signal edge rates are in the several
>hundred picosecond range.
>
>Those who believe that "good" PDS design will solve all signal via
>related crosstalk problems are woefully mistaken.
>
>
>
>
>Scott McMorrow
>Teraspeed Consulting Group LLC
>121 North River Drive
>Narragansett, RI 02882
>(401) 284-1827 Business
>(401) 284-1840 Fax
>
>http://www.teraspeed.com
>
>Teraspeed® is the registered service mark of
>Teraspeed Consulting Group LLC
>
>
>
>Perry Qu wrote:
>
>
>>Interesting topic. We recently had a design with a SDRAM interface consists
>>of 5 SDRAMs, 2 pairs clamshelled and one standalone. It's running on 155 MHz
>>clock single data rate so not a fast interface by today's standard. For the
>>clamshelled SDRAMs, we measured the address signals and the waveform on the
>>top and bottom sometimes are quite different, specifically, one of the SDRAM
>>(could be either top or bottom depending on which address pin we probe)
>>shows very visible crosstalk and worse shelf on edge. The result is less
>>margin for timing.
>>
>>This can't be caused by topology as we length-matched the trace from SDRAM
>>pin to the branch via in a mixture of star/far-end cluster topology. The
>>only thing I can think of is return current as most of the signals vias are
>>under the middle of the SDRAM packaging with no ground/power via really
>>closeby. The SDRAM packaging is not well done in my opinion as they have
>>most of the power/ground pins on one half of the chip, and very few
>>reference pins on the other half where all address pins locate. To make it
>>worse, the routing layer is all over the stackup and it can jump from a
>>layer close to top to a layer close to bottom and then jump back, with no
>>return vias close to signal vias, although they all reference to GND (we
>>have multiple GND planes throughout the stackup). The worse waveform seems
>>always occurs at the SDRAM with bigger jump in terms of reference planes
>>thus larger return loop area, which is the cause for crosstalk and higher
>>inductance on return and shelf on edge. I decide to add some ground vias
>>close to the signal vias for our next design which uses same chips.
>>
>>Regards
>>
>>Perry
>>
>>
>>=======================================
>>
>>Perry Qu
>>
>>Design & Qualification, Alcatel Canada
>>
>>600 March Road, Ottawa ON, K2K 2E6
>>
>>DID: 613-7846720 Fax: 613-5993642
>>
>>Email: perry.qu@xxxxxxxxxxx
>>
>>=======================================
>>
>>
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