[SI-LIST] Re: Current Return Vias

 Steve,
Can you explain what the term "quasi static extents" means?
I got to thinking why more stitching vias might be required as the signal
rise time decreases.
I like to visualize how the wavelength of a signal relates to distance on a
PCB and the phase differences that can occur.
If a signal has slow rise time, for example 3 ns, this means the rise time
equates to about 18 inches on a PCB.
If we take 1/10 of that distance which is 1.8 inches and there are one or
more stitching vias located within that distance then there is little phase
difference between the signal via and the stitching via. For a rise time of
100 ps, 1/10 of a wavelength would equate to 60 mils so the stitching vias
would have to be really close to do any good. Is this thinking valid and
doesit have any practical application or is it just an analogy or over
simplification? I can see you are looking at it in terms of S parameters,
butI wonder if the result is the same, the S parameters getting worse with
fewer stitching vais and faster rise times.

Joel



steve weir wrote: Lee, et-al I agree that there is a good deal of
misinformation that circulates on this subject. It is another topic that
ultimately comes down to the numbers. Single stitch vias are incapable of
"maintaining return path continuity". What they can do is act in concert
withother vias and planes, so that the net scattering has acceptably low
loss. From my experience path impedance continuity to high frequencies as
determined by low, linear S21 loss, and good S11 loss requires a pattern of
vias associated with each launch. Teraspeed designs such launches everyday.
But a return via pattern on a signal by signal basis eats up expensive real
estate far too quickly to be practical for managing routing layer
transitions. Usually we see these circumstances / effects from stitch vias:
For boards without either multiple Vss layers, or puddles, there is nothing
to stitch. It is down to bypass caps. For boards with multiple Vss layers
andmodest edge rates, the Vss vias of the bypass capacitors and components
are usually well within the quasi static extents. Additional stitch vias
directed at individual signals have very little impact. If for some reason a
PCB has a lot of open real-estate, ( more often test vehicles than real PCBs
) then the situation changes and distributing stitch vias provides
quantifiable benefits. For most practical designs the density and
distribution is usually OK without adding extra stitch vias. When in doubt,
do the homework. For boards with very fast edge rates, the quasi static
extents are small, and stitch vias associated with individual signals
displaymore pronounced effects. But, the dimensions become such that we
really have to throw away the quasi static model and look at the various
wavemodes. This requires a 3D full wave tool like HFSS, or CST. For really
fast signals, I reiterate that I cannot think of a case where one stitch via
associated with one signal could make the difference between acceptable and
unacceptable S parameter results. Either a pattern of vias is needed to make
the difference, ( sic launch ) or none at all. Regards, Steve. At 03:34 PM
7/24/2006, Lee Ritchey wrote: Ihsan, Well put. [Original Message] From:
IhsanErdin <erdinih@xxxxxxxxx>[1] To: <giovanni.guasti@xxxxxxxxxx>[2] Cc:
<si-list@xxxxxxxxxxxxx>[3] Date: 7/23/2006 7:36:40 AM Subject: [SI-LIST] Re:
Current Return Vias Giovanni, The EMC justification of a ground via in the
close proximity of a switching via is to minimize radial waves to the edges
of the card by providing a "return path" (I hate this phrase...) A two-wire
kind of transmission line -as you put it- would be another rationalization
against the impedance discontinuity for high-speed signals. In practice,
however, the placement of a ground via close enough to a switching via in
order to provide a matching impedance to -say 50 ohm- or to mitigate radial
wave propagation is in most cases -if not all- physically impossible. I
thinkthis kind of SI/EMI rule-of-thumbs are based on a qualitative
understanding of electromagnetic theory rather than rigorous research
results. In this context, I share Lee's stance to debunk these
recommendations because they have significant effect on the design cost by
closing routing channels and eating up on the valuable board real-estate. If
anybody has come across any research that states otherwise in a
peer-refereedpublication I'd like to hear that. Regards Ihsan On 7/22/06,
Giovanni Guasti <giovanni.guasti@xxxxxxxxxx>[4] wrote: Kenny, GND vias near
the signal are not dedicated to return currents, but they are often used to
optimize the impedance of the via. As the via is a short transmission line,
only the higher speed signals can benefit of the difference between an
optimized via and a "usual" via. You have to compare the higher frequency
component of your signal, its wavelength and the via length. This will give
you an idea of the effective needing to optimize this short transmission
line. Of course you could have a 133MHz signal with very sharp edges and
highfrequency components, even if it seems very unusual... In this case it
would be wise to choose a slower transmitter! The rule is to understand if
the via behaves like a transmission line for your signal or not, and in the
first case to do the best to reduce impedance discontinuities. Best regards,
Giovanni -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx[5]
[mailto:si-list-bounce@xxxxxxxxxxxxx[6]] On Behalf Of Lee Ritchey Sent: 22
July 2006 18:36 To: Kenny Frohlich; si-list@xxxxxxxxxxxxx[7] Subject:
[SI-LIST] Re: Current Return Vias Kenny, It is not true that you need a
"return current" via next to each layer changing signal via. I continue to
beamazed that engineers who are looked upon as SI experts say such things.
Imagine you have a 4 layer PCB, such as the mother board in a PC, where
thereare only two planes, one Vdd and one ground, where would such vias
connect? There have been billions of these made to date that work just fine
and have very fast signals on them. The return currents you are concerned
about find their way from plane to plane through the collection of
decouplingcapacitors and interplane capacitance that you had to engineer
intothe power delivery system in order to make it stable. Focus on this and
the return currents take care of themselves. EMI is minimized he same way..
[Original Message] From: Kenny Frohlich <kenny_frohlich@xxxxxxxxx>[8] To:
<si-list@xxxxxxxxxxxxx>[9] Date: 7/22/2006 6:45:56 AM Subject: [SI-LIST]
Current Return Vias Dear Experts, I understand that I need to provide ground
vias next to via explictly for the purpose of letting return currents jump
between layers. I know it's a requirement for high speed signals, especially
differrential signals. Is this also required for low speed single-ended
signals (133Mhz or slower)? =20 If this is a requirement, what would be a
good signal via to ground via ratio? For example, there are five signal vias
within a 1 inch area, how many ground vias do I need? =20 Thank you Kenny
=20__________________________________________________ Do You Yahoo!? Tired
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