[SI-LIST] Re: Current Return Vias

Chris,

This problem has been around for as long as I have been designing high
layer count PCBs.  If you use two thermal ties per plate through hole, you
meet both objectives.  If you connect the planes without them solderind and
unsoldering is very difficult.  IF you make no connections soldering is
great and SI is in the tank.

Almost all of my designs are 26 layers with many ground planes and this is
the method we use. 


> [Original Message]
> From: Chris Padilla \(cpad\) <cpad@xxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Date: 7/25/2006 8:53:52 AM
> Subject: [SI-LIST] Re: Current Return Vias
>
> I get push back all the time in trying to connect all "gnd" planes in
> multi-layer stackups (say 18 layers +...and usually at our limit of 26
> layers).  The reason is provide by the manufacturing folks in that they
> cannot solder or get good solder flow because the mulitple gnd planes
> act like heat sinks.  Therefore, I am forced to used thermal reliefs and
> even in a lot of cases, I cannot even connect some gnd planes to the gnd
> vias!
>
> Any thoughts on this subject?
>
> Thanks,
>
> Chris Padilla
> Cisco Systems
> San Jose, CA=20
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lee Ritchey
> Sent: Monday, July 24, 2006 3:44 PM
> To: Joel Brown
> Cc: Kenny Frohlich; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Current Return Vias
>
> Joel,
>
> First, you should have stitched your ground planes to each other every
> where there is a ground pin on a device, so these ground planes should
> be well tied to each other every place you have a component whether it
> be a bypass capacitor or an IC.  (This argues for spreading your bypass
> capacitors  evenly around the planes as has been advocated by a number
> of members of this forum in the past.)  Only where you might change
> layers in an empty part of the PCB is this not so. Second, when you
> engineer your PDS you need to insure that the impedance is a few
> milliohms across all of the frequencies in your signals, so the Vdd
> planes are "shorted" to these ground planes by this method.  ( To
> achieve this low impedance across the broad range of frequencies in your
> signals, you will be using plane capacitance as well as a variety of
> different values of capacitors.  When done right, all of the planes are
> "shorted" to each other and return currents have all the paths they
> need.  If the PDS isn't properly designed you can wind up with EMI
> problems and unstable logic operation.
>
>
> > [Original Message]
> > From: Joel Brown <joel@xxxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>
> > Cc: Kenny Frohlich <kenny_frohlich@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > Date: 7/23/2006 12:25:04 PM
> > Subject: [SI-LIST] Re: Current Return Vias
> >
> >  I am currently working on board that has 12 layers.
> > Ground planes are layers 2, 5, 8, and 11.=20
> > If a high speed signal changes from layer 3 to layer 9 then its=20
> > reference planes change from layers 2 &5 to layers 8 &11.
> > Since the return current flows under the signal trace on the reference
> plane
> > , this return current has jump from from one set of planes to the=20
> > other
> set
> > at the point signal changes layers through a via. The return current=20
> > could jump through interplane capacitance or through a ground via=20
> > located next
> to
> > the signal via. So in this situation I don't see why having a ground=20
> > via nextto a signal would not be beneficial? Does the interplane=20
> > capacitance provide a lower impedance path than the ground via for the
>
> > return current
> method to
> > jump planes? Please enlighten me.
> > Joel
> >
> >
> > Lee Ritchey wrote: Kenny, It is not true that you need a "return
> current"
> > vianext to each layer changing signal via. I continue to be amazed=20
> > that engineers who are looked upon as SI experts say such things.=20
> > Imagine you havea 4 layer PCB, such as the mother board in a PC, where
>
> > there are only twoplanes, one Vdd and one ground, where would such=20
> > vias connect? There
> have
> > been billions of these made to date that work just fine and have very=20
> > fast signals on them. The return currents you are concerned about find
>
> > their
> way
> > from plane to plane through the collection of decoupling capacitors=20
> > and interplane capacitance that you had to engineer into the power=20
> > delivery system in order to make it stable. Focus on this and the=20
> > return currents takecare of themselves. EMI is minimized he same way..
>
> > [Original Message]
> > From: Kenny Frohlich <kenny_frohlich@xxxxxxxxx>[1] To:
> > <si-list@xxxxxxxxxxxxx>[2]Date: 7/22/2006 6:45:56 AM Subject:=20
> > [SI-LIST] Current Return Vias Dear Experts, I understand that I need=20
> > to provide
> ground
> > vias next to via explictly for the purpose of letting return currents=20
> > jump between layers. I know it's a requirement for high speed signals,
> especially
> > differrential signals. Is this also required for low speed=20
> > single-ended signals (133Mhz or slower)? If this is a requirement,=20
> > what would be a good signal via to ground via ratio? For example,=20
> > there are five signal vias within a 1 inch area, how many ground vias=20
> > do I need? Thank you Kenny=20
> > __________________________________________________ Do You Yahoo!?=20
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