[SI-LIST] Re: Crosstalk FastHenry - ( Hspice Inverter Modeling )
- From: "Abe Riazi" <ARIAZI@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 27 May 2003 21:45:24 -0700
Manthos labropoulos Wrote:
>What do you mean when you say:
> you should be able to use an inverter in Hspice
> (and connect it to a distributed RLC model)
> however, it is necessary to ensure that for the
> driver side
> you are connecting to an output node of the model
> and for
> receiver side you are connecting to an input node
> of the
> inverter.
>
Dear Matheos:
In order to clarify my statement, I have produced a Hspice netlist which
includes an inverter subcircuit plus driver and receiver models
which utilize that subcircuit. It is pasted below:
****************************************************
*********** A Topology with Inverters ***************
*
.global vdd
.option post
.inc 'tsmc-035.tech'
vdd vdd gnd dc 3.3V
*
****Define inverter subcircuit
.subckt inv in out
MN1 out in gnd gnd cmosn L=0.35u W=0.7u
MP1 out in vdd vdd cmosp L=0.35u W=1.4u
.ends inv
*
* ***Define the circuit topology
Vin driver_in 0 pulse(0 3.3v 0 200p 200p 0.3n 1n)
X_U1 driver_in driver_out inv
Ro_driver driver_out driver_rout 50
T1 driver_rout 0 receiver_in 0 Zo=50 TD=0.2p
X_U2 receiver_in receiver_out inv
R_load out_U2 0 50
*
.TRAN 0.1n 2n
.END
*
*********************************************************
To run above netlist you also need a file called " tsm-035.tech "
This file which specifies the model technology for the TSMC-0.35u
process can be downloaded from:
www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html
We can think of this netlist as a single net topology containing
two integrated circuits U1 ( driver) and U2 (receiver).
The driver output resistance Ro is set at 50 Ohms. The same value is also
assigned to characteristic impedance of a transmission line T1 and also the
load resitance R_load. T1 illustrates how to connect the output node of
driver to the input of receiver.
A wrong way of connecting the two ICs would have been:
T1 driver_rout 0 receiver_out 0 Zo=50 TD=0.2p
because the output of driver is now connected to output of receiver
(rather than the receiver input).
You can replace the impedance and delay values of T1 with values desirable
to your case. It is also possible to substitute for T1 a distributed line
model consisting of a chain of RLCG (or RLC or LC) segments, but this
involves some additional effort to compute the optimum number of sections
and the correct values for R, L, C and G elements.
An interesting exercise is to execute the attached Hspice netlist
and plot voltages at the nodes " driver_in " , " driver_out " , "
receiver_in" and " receiver_out". A comparison of waveforms at
" driver_in " with " driver_out " and " receiver_in" with " receiver_out"
would then reveal how the inv subcircuit functions as an
inverter.
In closing, I would like to emphasize that main purpose of this example is
to demonstrate a way of modeling and connecting inverters in Hspice. I am
not certain how closely the various parameters used in this illustration
(e.g. TSMC-0.35u technology, the 200pS excitation rise time, 50 ohm line
impedance , etc.) fit your particular application.
Best Regards,
Abe Riazi
ServerWorks
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