*From*: manthos labropoulos <manthoslmp@xxxxxxxx>*To*: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>*Date*: Sat, 24 May 2003 23:01:21 +0100 (BST)

Dear Mr Riazi Thanks for your comments. What do you mean when you say: > you should be able to use an inverter in Hspcie > (and connect it to a distrbuted RLC model) > however, it is necessary to ensure that for the > driver side > you are connecting to an output node of the model > and for > receiver side you are connecting to an input node > of the > inverter. Tha point is that the distortion of the signal and the propagation delay are very big and it seems that the model of the resistor (as the driver) and the capacitor (as the receiver) are far away from each other. (Is it like this or am i wrong ?) Can you give me an example of an inverter (values of W and L) which can drive a long interconnect (e.g 2000um) in a high frequency (e.g 1GHz) ? Thanks a lot. Matheos --- Abe Riazi <ariazi@xxxxxxxxxxxxxxx> έγραψε: > Dear Matheos : > > My response to some of your questions are shown > below: > > >As i told you before in my simulations i was using > the > >equivalent output resistance of the driver and the > >equivalent capacitance of the receiver. > >Now i tried to do the simulations while using the > >actual circuit of an inverter in Hspice. In that > case > >i couldn't take proper results and i don't know > why. > >Do you have an idea why when i am connecting (to > the > >distributed RLC model) an inverter as a driver and > an > >other one as the receiver i can't take results from > >the simulations (the output are actually either to > gnd > >or to the Vdd) ? > > you should be able to use an inverter in Hspcie > (and connect it to a distrbuted RLC model) > however, it is necessary to ensure that for the > driver side > you are connecting to an output node of the model > and for > receiver side you are connecting to an input node > of the > inverter. > > >Moreover i would like to ask you why most people > >(including me) are not taking into account the > >conductance G during the simulations for the > >interconnects. The point is that FastCap and > FastHenry > >are not ging me any values for the conductance. Is > my > >approximation (only for RLC values) correct ? > > Obviously the analyses is simpler if one can > ignore the dielectric loss. Sometimes there is > jusitification for ignoring this loss. For, example > when modeling a coax with expanded teflon > dielctric, G is often ignored because teflon is a > very > low loss dielctric. For FR-4 based PCBs with > non-zero dielectric, the G part usually needs to be > taken > into consideration to produce accurate results. > When the trace length is short and/or > the signal rise/fall time is slow, then again the > effect of > dielectric loss (and also conductor loss R) can > prove > negligilbe. > > > >As regards the loop inducatance , i would like to > ask > >you how can loop inductance be ussed in a Spice > model > >in order to perform simulations for the crosstalk. > >In my methodology i am extracting the partial > >inductances for the conductors (including the Vdd > and > >the Gnd conductors outside the signal lines, which > are > >supposed to be the Vdd and the Gnd return paths. > >Remember that i don't have ground plane but an > >orthogonal layer below them) and i am making the > >equivalent distributed model in Spice. > >How can the loop inductance be used in order to > make > >the equivalent spice model for the case that we > have a > >ground plane and the signal lines above it (in this > >case the return path is supposed to be through the > >ground plane)? > > You can utilize loop inductance for Hspice crosstalk > analyses > by first incorporating the loop indctance into a > RLGC file; > then creating a mult-line W-elemet transmission > line model which utilizes that RLGC file. > > >One last thing is that from my simulations with the > >model i discribed you, i odserved the following > >things. > >When the we have skews in the same direction in > >adjacent lines then the ringing is very big (e.g > >H-H-H-H-H .. where H is a 0-1 transition and L is > an > >1-0 transition) > >On the other hand when we have opposite skews in > the > >signal lines (e.g H-L-H-L-H ...) then the ringing > is > >almost ZERO(0) !!!! > >Can you please expain this to me ? > >Is there anything wrong with my simulations or does > it > >have to do with the return current paths which in > the > >second case are extinguising the ringing ? > > For the H-H-H-H-H ..case the net loop inductance > is very high (becasue magnetic fileds of neighboring > lines reinforce each other). For the case H-L-H-L-H > ... > the net loop inductance is relatively small 9becasue > there is cancelation of magnetic fields). > Subsequently, the effect you are seeing for the two > cases > is problably due to the difference in the return > path. > > Best Regards, > > Abe > > -----Original Message----- > From: =?iso-8859-7?q?manthos=20labropoulos?= > [SMTP:manthoslmp@xxxxxxxx] > Sent: Tuesday, May 13, 2003 9:11 AM > To: Abe Riazi > Subject: RE: Crosstalk FastHenry > > << File: ATT00022.txt; charset = iso-8859-7 >> > ____________________________________________________________ Do You Yahoo!? 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