[SI-LIST] Re: Coupling THROUGH a plane?

Dear Boris,

What is the speed of the LVDS signal and of the three CMOS signals on the
other side of the ground plane? How thick (ounces) is your ground plane?
May I assume low impedance drivers on one end of each CMOS signal and an
open (shunted by some capacitance) at the other end?

Regards,

Paul
_____________________

Boris Yost wrote:
> Dear List:
> 
>       I'm working on a persistent annoying bit error with LVDS.  We had one
> design that we made hundreds of and never had a problem.  We copied the LVDS
> receiver part (same parts and same layout) to a new design.  Now I have a
> bit error on both ordinary and torture test patterns that shows up on 10% of
> boards.  I have tracked it down to one particular symbol, and it turns out
> that symbol has a dip of about 40% of signal swing in common mode voltage.
> The eye diagram of the difference signal is wide open.
>       Now, while we copied exactly the LVDS, we didn't copy everything else.
> Turns out, they put about 3 ordinary CMOS traces under the victim signal.
> However, the victim and my supposed aggressors are separated by a solid
> ground plane.  (That is, it is as solid as anybody's ground plane ever
> is--except for the via holes.)  The LVDS traces are on the surface, and the
> other traces are on layer 3 of a 6 layer board.  The board that works
> doesn't have traces there.
>       Should I be looking hard at this difference, or should I be looking at 
> our
> many other potential problems.
> 
> Best regards,
> Boris Yost
> Mgr Electrical Engineering
> Rainbow Displays
> 
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> 


-- 
Paul Levin
Senior Principal Engineer
Xyratex Storage Systems

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