[SI-LIST] Re: Coupling THROUGH a plane?

Boris,

As you said,

"I have tracked it down to one particular symbol, and it turns out that symbol 
has a dip of about 40% of signal swing in common mode voltage."

If the error is correlated to a symbol, then unless the CMOS signal transitions 
are also correlated to this particular symbol, you should look elsewhere for 
your problem.  Above around 20 MHz even a 1/2 oz copper plane is greater than 
one skin depth in thickness. Isolation above this frequency is greater than -60 
dB.  At LVDS signaling rates there is insignificant coupling though the plane 
to be a problem.

I would look in another area.  You said that the layout was the same for the 
receiver.  How about the stackup.  Is it the same?  Power supply decoupling?  
Connectors and pinouts?  Via locations and coupling to adjacent signals?  
Reference voltage filtering?  Do you have just one LVDS circuit or multiple 
circuits?  If multiple circuits, do they all have bit error problems?  Do you 
see the same common mode droop on both the "good" and the "bad" boards with the 
same symbols, when measuring them externally at the same point?


best regards,

scott



-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com




Boris Yost wrote:

>Dear List:
>
>       I'm working on a persistent annoying bit error with LVDS.  We had one
>design that we made hundreds of and never had a problem.  We copied the LVDS
>receiver part (same parts and same layout) to a new design.  Now I have a
>bit error on both ordinary and torture test patterns that shows up on 10% of
>boards.  I have tracked it down to one particular symbol, and it turns out
>that symbol has a dip of about 40% of signal swing in common mode voltage.
>The eye diagram of the difference signal is wide open.
>       Now, while we copied exactly the LVDS, we didn't copy everything else.
>Turns out, they put about 3 ordinary CMOS traces under the victim signal.
>However, the victim and my supposed aggressors are separated by a solid
>ground plane.  (That is, it is as solid as anybody's ground plane ever
>is--except for the via holes.)  The LVDS traces are on the surface, and the
>other traces are on layer 3 of a 6 layer board.  The board that works
>doesn't have traces there.
>       Should I be looking hard at this difference, or should I be looking at 
> our
>many other potential problems.
>
>Best regards,
>Boris Yost
>Mgr Electrical Engineering
>Rainbow Displays
>
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