[SI-LIST] Re: Copper losses

  • From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
  • To: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
  • Date: Fri, 12 Aug 2011 15:30:46 -0700

Jeff,

You bring up several good points.  At the top of the list is the lack of any 
common language to describe copper roughness, either at provided by the foil 
manufacturer and as etched by the fabricator.

We have our hands full!

How does one achieve repeatability with such a confusing environment?

Lee

--------------------------------------------------
From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
Sent: Friday, August 12, 2011 1:28 PM
To: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Copper losses

> Hello Lee,
> I changed the subject to reflect the topic.
> I look forward to hearing what you find out; we're conducting similar 
> studies.  Some things I would bring up:
> 1) I would hesitate to generalize data from one supplier and/or 
> manufacturer to anything more than that. In my experience, there is a 
> large variation among either of those. For instance, I don't know that 
> there's a standard meaning of "standard", "rtf", "lp", "vlp", etc.  If 
> someone knows otherwise, I'd love to see it.  I'm not even sure we know 
> exactly how to describe roughness in terms that translate directly to 
> insertion loss (see our paper on copper texture at:
> http://www.designcon.com/2010/DCPDFs/5-TA2_Paul_Huray.pdf).
> 2) You'll need to include effects of your manufacturer's "micro-etching" 
> process, if any.  You can start with beautifully smooth copper, but end up 
> with very rough texture as the manufacturer etches it to promote better 
> adhesion.  It muddies the waters beautifully.
> 3) Be sure to specify which direction the smooth side of the copper faces 
> and how it's kept smooth.  That side may not be one you think (drum side), 
> depending on processing.
> 4) Keep in mind that microstrip is a different beast.  Even if you specify 
> VLP for the rest of your design, you may end up with "standard" on the 
> outer layers, for better peel strength.
> 5) Likewise, microstrip is processed very differently than stripline 
> (obviously; it's plated, for one thing); its behavior may be heavily 
> influenced by processing, regardless of what copper type you started with.
> 6) Can you share how you intend to verify the structural integrity of each 
> copper type?  It's one thing to get very low loss, but you also need to 
> have a board that doesn't fall apart either during or after processing.
> 7) Once you figure all this out, another challenge is to phrase a fab 
> drawing such that multiple vendors will follow similar material selection 
> (including copper) and processing, ensuring equivalent insertion loss, 
> regardless of vendor.
>
> I believe it will take years to peel this onion; we've only just begun...
> Cheers,
>
> Jeff Loyer
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] 
> On Behalf Of Lee Ritchey
> Sent: Friday, August 12, 2011 10:53 AM
> To: Al Neves; 'Havermann, Gert'; 'JASON MILLER'
> Cc: 'Hermann Ruckerbauer'; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: AW: Re: Fiber weave effect modeling: Stack of 
> materials ...
>
> Al,
>
> Sounds good.  Glad to help.  At the moment, Isola is the only laminate
> supplier actively trying to help us all solve these problems.
>
> As we speak, I am building a series of test PCBs using four different 
> Isola
> materials.  Each test PCB is 16 layers with a total of 6 stripline layers.
> These are divided into two groups of three.  Both groups have the same set
> of test traces.  One group has the smoothest copper we can process and the
> other group has the "standard" copper roughness.  When we are finished, I
> hope to have data that will allow us to reliably specify copper losses.
> Wouldn't that be nice!  Be a lot better than the current "trial and error"
> approach being used.
>
> Hope to have data in time for DesignCon.
>
> Lee
>
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