[SI-LIST] Re: Copper Pours

Howdy,
I do not even pretend to be an SI expert.  <=That can also translate to I know 
just enough to be dangerous.  However, I (unfortunately?) like the look of the 
ground fill most of the time.
I stitch the fills on a 1mil grid, to avoid copying a pattern and pour them at 
no less than having a clearance of 25mils from all other copper or five times 
the distance to the reference plane, whichever is greater.

Anyone have the time to poke holes?
I know, another possibly dangerous rule of thumb.  But that practice has been 
done on designs that have data or clock speeds well under the 500MHz range and 
only when requested.  I have never received any negative feedback, yet to see a 
poor quality signal, or caused the loss a customer.
Maybe I should try to account for impedance controlled traces using the 
asymmetric stripline trace portion vs. the embedded microstrip portion of a 2D 
field solver when those traces are rarely on the next inner layer.
It's all that I have available.  I know that I am just asking for a lashing...

For designs into the GHz range and above, I have successfully referred the 
advise of and worked with a signal integrity specialist.

In any case, I thank all of you for sharing your previous and future posts as 
well as letting me be a part of this forum for so many years even though I have 
not contributed to its database.

Cheers!
Drew

----- Original Message ----- 
From: Dennis Han
Cc: si-list@xxxxxxxxxxxxx
Sent: Monday, April 24, 2006 6:43 PM
Subject: [SI-LIST] Re: Copper Pours



I think this is one of those 2-layer board rules that people applied to
multilayer boards without thinking about it.  The reason some people think
copper pours are beneficial is there are still many boards designed with no
transmission line rules whatsoever.  The pours when done incorrectly, and
most are, lower the impedance of the transmission lines to the point the
lines are now matched to drivers that are in the 20-40 ohm range.  This
helpsthe overall design, but there are still many impedance discontinuities.
Also, the copper pours have reduced EMI most of the time just because the
transmission line impedances are reduced enough that the discontinuities are
less destructive and lower impedances radiate less.  The pours also tend to
cover up poorly designed reference planes, especially power planes.  The
pours are unnecessary when a board is designed properly.

Dennis


Lee Ritchey wrote: Robert, Using copper pours in signal planes to reduce EMI
is one of those may urban legends that are not true. You are correct about
their potential negative effective on signals. Who starts these strange
rules, anyway? [Original Message] From: <Robert.Havlik@xxxxxxxxxxxx>[1] To:
<si-list@xxxxxxxxxxxxx>[2] Date: 4/22/2006 1:26:08 PM Subject: [SI-LIST]
Copper Pours I understand copper pours are commonly used on PCB&#8217;s for
EMC shielding, power supplies, and in analog designs, but I have not found
any resources with good advice on when a copper pour should or should not be
used. I can see that placing a copper pour connected to a ground plane
aroundhigh speed signal traces would reduce EMI and also possibly signal
coupling, but it also seems that having a ground in close proximity to a
signal trace it could also change the characteristic impedance of the
transmission line. If the copper pour is not a uniform distance around the
trace, it seems it could potentially cause impedance discontinuities. Also,
Ihave seen both hatched and solid pours, and I have not seen anything on the
advantages and disadvantages of either approach or in what circumstances one
should be used over the other. Any advice on copper pour usage or good rules
of thumb would be greatly appreciated. Thanks. -Robert Havlik University of
Colorado, Boulder
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