[SI-LIST] Re: Convergence problem with DDR DRAM IBIS model

Hello, Ravinder,

Maybe you could check the following:
If the Xtalk geometry window coverage whether it's too large, and use
comprehensive simulation mode. it maybe large.
then check the tlsim.log file to see the detail.

Best regards,
Joseph

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ravinder.Ajmani@xxxxxxxxxxxxxx
Sent: Thursday, June 21, 2007 12:55 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Convergence problem with DDR DRAM IBIS model

I am running IBIS simulation on a 32-bit DDR1 point-to-point interface.
In case of one DRAM vendor, the simulator reports errors due to
convergence problem under Typical simulation on 22 Data bits and 4 DQS
bits when DDR is driving.  There is no problem with remaining 10 bits in
Typical, or all the bits in Fast and Slow simulation.  I have run
similar simulation with two other vendor part, and a die-shrink part
from the same vendor without any problems.  I am baffled with these
selective errors.  I have looked at the package parasitic and do not see
anything unusual.  Has anyone else seen this kind of problem.
Thanks.

Regards,
Ravinder Ajmani
Server PCB Development
Hitachi Global Storage Technologies


Email: Ravinder.Ajmani@xxxxxxxxxxxxxx

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