[SI-LIST] Convergence problem with DDR DRAM IBIS model

From: Ravinder.Ajmani@xxxxxxxxxxxxxx
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 20 Jun 2007 09:55:03 -0700

I am running IBIS simulation on a 32-bit DDR1 point-to-point interface. In 
case of one DRAM vendor, the simulator reports errors due to convergence 
problem under Typical simulation on 22 Data bits and 4 DQS bits when DDR 
is driving.  There is no problem with remaining 10 bits in Typical, or all 
the bits in Fast and Slow simulation.  I have run similar simulation with 
two other vendor part, and a die-shrink part from the same vendor without 
any problems.  I am baffled with these selective errors.  I have looked at 
the package parasitic and do not see anything unusual.  Has anyone else 
seen this kind of problem.
Thanks.

Regards, 
Ravinder Ajmani
Server PCB Development
Hitachi Global Storage Technologies


Email: Ravinder.Ajmani@xxxxxxxxxxxxxx

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Follow-Ups:

[SI-LIST] Re: Convergence problem with DDR DRAM IBIS model
From: Lynne D. Green

[SI-LIST] Re: Convergence problem with DDR DRAM IBIS model
From: Joseph Kao

[SI-LIST] Convergence problem with DDR DRAM IBIS model

Other related posts: