[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR
- From: Tadashi Arai <arap@xxxxxxxxxxxxxx>
- To: "[SI-LIST]" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 18 Oct 2002 09:37:56 +0900
Hi Jack,
According to public opened document;
Intel(R) Pentium(R)4 Processor in 478-pin Package and Intel(R) 845
Chipset Platform for DDR Design Guide (Feb. 2002, Doc#29805-002)
Section 5.3.1.2.2 "Strobe to Clock Length Matching Requirements",
Constraints what you said between CK and DQS are described as
followings;
- SCK/SCK# Length = X
- SDQS Length = Y, where (X - 2.0") <= Y <= (X - 1.0")
It is not so curious, isn't it?
Regards,
On Thu, 17 Oct 2002 17:54:42 +0800
"Jack W.C. Lin" <JackWCLin@xxxxxxxxxxxx> wrote:
>
> Hi John:
> Thanks for your reply. But I think it is too dangerous for such =
> constraint
> like Intel, say X-4.4<=3DY. This is a lower bound constraint for DQ/DQS =
> or
> upper bound constraint for CK/CK#. We all know that it is impossible to
> implement another delay mechanism in the DDR memory cell, for more =
> accurate
> data latched by internal device in the cell, it should put a constraint =
> like
> X-4.4<=3DY<=3Dsome value, that will more make sure that data arrived =
> later than
> clock for internal device in the memory cell, isn't it?=20
>
>
> Jack
>
> -----Original Message-----
> From: John Phillips [mailto:John.Phillips@xxxxxxxxxxxxxx]=20
> Sent: Thursday, October 17, 2002 5:05 PM
> To: Jack W.C. Lin; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR
>
>
> Once DQS latches the DQ at the input to the part, the device must then
> synchronise the data to its local clock. If the clocks between say the =
> NB
> and the DDR memory devices are to far out of alignment, it will not be
> possibble to compensate for this mis-alignment in the recieving device. =
> This
> will mean that the data cannot be properly sampled in the local devices
> recieving clock domain.
>
> Best Regards
>
> John
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx=20
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jack W.C. Lin
> > Sent: 17 October 2002 09:32
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR
> >
> >
> > Hi All SI friends:
> > I met a question about DDR. We all know that DDR is a source=20
> > synchronus structure, data transfer will not depend on bus clock any
> > more. In chip
> > design, there exist Delay mechanism for DQ and DQS (90 degree
> > phase shift)
> > which is controlled by bus clock. But we found that either in
> > Intel 845 chip
> > series or AMD K8 =A1K., they all have some layout constraint on
> > DQ/DQS and
> > command clock (CK&CK#). For example in Intel, if DQ/DQS
> > length is Y, CK/CK#
> > is X, then they should follow X-4.4<=3DY. In AMD, Y=3DX+0.5 or
> > Y=3DX-0.5. Why? In
> > DDR mechanism, it seems no reason to put such constraints on
> > them. Maybe I
> > miss something, is there anyone could provide a reasonable
> > explanation?
> > Thanks
> >
> > Jack
> >
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//// /// // / / / / / / / / / /
Tadashi Arai//Platform Design Dept.,Mobile Computing Div. Fujitsu Limited
arap@xxxxxxxxxxxxxx TEL:+81-42-370-7624 Ohmaru, Inagi-shi, Tokyo, Japan
/ / / / / / / / / / / // ////
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