[SI-LIST] Re: Constraints on DQ/DQS and CK/CK# in DDR

Gentlemen,

I have implemented a small four word FIFO in my DDR controller for crossing 
what is
essentially a separate clock domain (DQS) back to my internal memory clock 
domain
(that's what you do to cross clock domains no?)!  That gives me plenty of 
margin for
data turn around and delay of the data across the bus on the return path.  
That's
how I compensate for the alignment of the data with my internal clock.  As far 
as
aligning the DQS with the DQ and the 90 deg shift, most would agree you need 
some
sort of compensated delay line on the DQS and that the DQS and DQ signal paths
should all be matched on the board to match skew as best possible.

Hope this helps, keep in touch as you work through the DDR Controller 
development!

Eric

John Phillips wrote:

> Once DQS latches the DQ at the input to the part, the device must then
> synchronise the data to its local clock. If the clocks between say the NB
> and the DDR memory devices are to far out of alignment, it will not be 
> possibble
> to compensate for this mis-alignment in the recieving device. This will mean
> that the data cannot be properly sampled in the local devices recieving clock
> domain.
>
> Best Regards
>
> John
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jack W.C. Lin
> > Sent: 17 October 2002 09:32
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Constraints on DQ/DQS and CK/CK# in DDR
> >
> >
> > Hi All SI friends:
> > I met a question about DDR. We all know that DDR is a source
> > synchronus
> > structure, data transfer will not depend on bus clock any
> > more. In chip
> > design, there exist Delay mechanism for DQ and DQS (90 degree
> > phase shift)
> > which is controlled by bus clock. But we found that either in
> > Intel 845 chip
> > series or AMD K8 ¡K., they all have some layout constraint on
> > DQ/DQS and
> > command clock (CK&CK#). For example in Intel, if DQ/DQS
> > length is Y, CK/CK#
> > is X, then they should follow X-4.4<=Y. In AMD, Y=X+0.5 or
> > Y=X-0.5. Why? In
> > DDR mechanism, it seems no reason to put such constraints on
> > them. Maybe I
> > miss something, is there anyone could provide a reasonable
> > explanation?
> > Thanks
> >
> > Jack
> >
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--
Eric Deys
Senior IC Design Engineer
Video Products Division
Gennum Corporation
3430 South Service Road
Burlington, L7N 3T9
edeys@xxxxxxxxxx
(905) 632-2999 x 3200


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