[SI-LIST] Re: Connexion FPGA-memory

Philippe,

There is more information needed to answer this question.

The problem with connecting several devices on the single net is likely
to be putting too many loads on the nets and thus violating the time
constraints of the memory receivers. That is, you data signal may not
settle by the time your next clock arrives.

One -- drive strength of your FPGA. You can request an IBIS or SPICE
model from the FPGA vendor so you need how your FPGA memory driver
behaves and what kind of V/I and V/t curves it will produce, especially
under heavy load.

Second -- length of the net. When you place multiple devices on the real
PCB, they will be physically far from each other. The length of the
memory net will define the flight time, and that will add to the net
delay.

Third -- your memory bus is likely bi-directional. Same problem applies
to your memory chips -- they need to be able to drive the bus and fit
within the settling time on the FPGA receiver.

For a complicated problem like that, I would recommend a simulation tool
that will properly incorporate transmission line parameters, like
impedance and length, and that will be able to work with IBIS or SPICE
models that you memory/FPGA vendor will provide you.

Mike

-----------------------------------------------------------------
Michael Khusid
Ansoft Corporation
HF/SI Application Engineer
 
25 Burlington Mall Road, 6th floor
Burlington, MA 01803-4100
 
Tel 781-229-8900 Ext. 34
Fax 781-229-8624
--------------------- http://www.ansoft.com ---------------------
 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Philippe Robert
Sent: Monday, June 24, 2002 10:49 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Connexion FPGA-memory

Hello there,

I am designing a PCB and I need to connect an FPGA to some memory.
Memory
devices are all 16bits x 64Meg devices. The aim is to make a 16-bit bank
as
big as possible. 
I need to work out the maximum number of devices the FPGA can drive.
The output capacitance of the FPGA is 35pF
The input capacitance of the memory is 4pF.

Could someone help me to work the number of memory devices that I can
connect to the FPGA ?


Thanks a lot.
Philippe.


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