[SI-LIST] Re: Common Clock and Source Synchronous Timing Margins

Hi all,

There were a lot of parts to this thread, but I wanted to comment on:

(5) The Interconnectix (ICX) simulator also provides a means for
automatically compensating for the load difference between the test load and
the actual PCB trace load.

>> I think most, if not all, of the IBIS simulators have this capability.
The different vendors give it different names and have somewhat different
options, but it's basically the same concept with different implementation
details.

But this method depends, of course, on the manufacturer to supply the
appropriate test load parameters. Since the IBIS model, on which ICX
simulations are based, assumes a certain configuration of test capacitance
and resistance, this presents a problem where the manufacturer uses a
different configuration. For example, I encountered a manufacturer who
claimed he used a current-source test load, with a different current load
for the high and low states of the tested outputs. I had to use
approximations in order to be able to simulate these outputs using an IBIS
model. Has anyone encountered such a problem and have a solution?

>> First and foremost, you're doing the right thing, and that is paying
close attention to the correlation between the manufacturer's spec and
what's in the IBIS model.  The situation you describe is one common problem,
spec'ing a high speed part into a large capacitive (lumped) load is another
common one.

>> For your specific case, the easiest solution may be to disable the
simulator's buffer delay adjustment and report the raw data instead.  You
then simulate the different test load conditions individually, determine the
adjustment factor for each case and adjust the raw data in whatever manner
you like (as in, Excel).  Alternatively, some tools allow you to load the
delay adjustments into the library directly, and use these values to perform
the correction.

>> The base problem you identified - limitations of the existing IBIS spec
in specifying test loads, is, I believe, a recognized issue.

Hope that helps,

Todd.

Todd Westerhoff
SI Engineer - Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@xxxxxxxxxxx - ph: 978-671-5084
============================================

"Oh, but ain't that America, for you and me
 Ain't that America, we're something to see
 Ain't that America, Home of the Free
 Little pink houses, for you and me"

- John Mellencamp



------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: