[SI-LIST] Common Clock and Source Synchronous Timing Margins

Dear Scholars:

The need for "common-clock" and "source synchronous"  timing analyses, 
arises regularly in pre-route and post-route simulations of  high speed PCBs.

In a "common-clock" approach, with bus driver and receiver sharing 
the same clock, the setup and hold timing margins are often governed by:

Tsetup_margin = Tcycle - Tpcb_skew - Tclock_skew - Tjitter - Tco_data 
     - Tflt_data - Tsetup          

Thold_margin = Tco_data + Tflt_data + Tclock_skew + Tpcb_skew - Thold   

Common clock timing techniques are limited to  medium speed (e.g. frequencies
below ~ 200 or 300 MHz) buses [Reference 1]; therefore, at higher 
frequencies another means such as source synchronous signaling can be required.

In the source synchronous scheme the same driver chip is used to send the 
data and strobe signals to the receiver, with strobe signal usually transmitted 
a
short time after transmission of data bits. Applicable formulas include:

Tsetup_margin = (Tco_strobe - Tco_data) +  (Tflt_strobe - Tflt_data ) + Tdelay 
- Tsetup 

Thold_margin = (Tco_data - Tco_strobe ) + (Tflt_data - Tft_strobe) + Tdelay - 
Thold

In above equations Tcycle represents cycle time (clock period) and, 

Tpcb_skew = PCB flight time skew ( for clock traces).
Tco_data =  Driver's data output valid delay (at pad). 
Tclock_skew = The output clock buffer skew.
Tjitter =  Cycle to cycle variations of clock period.
Tflt_data =  Data PCB trace (from driver to receiver) propagation delay.
Tdelay = Offset between data and strobe.
Tco_strobe = Driver delay of the strobe (at pad).
Tflt_strobe = Flight time of strobe interconnect.
Tsetup = Receiver's input set up requirement (at pad).
Thold = Receiver's hold time requirement (at pad).

Certain parameters (such as Tco ) are usually obtainable from data sheets,
whereas determining the data and strobe flight times (e.g. Tflt_data and 
Tflt_strobe)
requires simulation.

System flight time corrections are frequently necessary to avoid double 
counting of
 driver rise and fall times and to compensate for system loading effects.  This
 implies subtracting the rising/falling delays of the buffer driving into the 
standard 
test load [ References 2 and 3] from the PCB driver to receiver propagation 
delay.
However, this correction may be also accounted for by the simulation program. 
For example,  XNS has an enable option for automatic subtraction of driver's
 TIME_TO_VM  before reporting the rise and fall times. 

The Excel program is quite popular for processing and presenting timing
simulation results.  A timing spreadsheet can include a listing of simulated
buses (nets), driver and receiver nodes, flight times and setup and 
hold margins, etc.

In order for the data to be timely latched in,  it is essential
to avoid violating the receiver's setup and hold requirements. If
a net indicates negative setup (or hold) margins, then it is necessary
to ascertain the cause of  timing violation (this often involves careful 
examination of associated waveforms) and ways of eliminating
the problem. 
 
Although, there are usually more than one approach for fixing
system timing problems, setup margin failures are frequently repaired
by shortening the driver to receiver data trace.  Similarly, negative 
hold margins are often eliminated by lengthening the data line.

 As signal frequencies/edge rates get faster, effects due to non-ideal 
return paths, SSO, ISI, noise, etc. can  significantly increase skew 
and complicate utilization of source synchronous technique.
Several alternative ways of bus signaling  aimed at minimizing 
skew effect are discussed in Reference 1.

In closing, the common clock and source synchronous formulas 
provide a means for monitoring those timing elements critical
to system performance, maximum allowable speed,  and setup/hold
budgets.  Timing spreadsheets in conjunction with waveform
analyses are commonly applied to identify the causes of failed 
setup/hold margins and means of eliminating these violations.

REFERENCES:

1. Stephen H. Hall, Garrett W. Hall, James A. McCall, "High Speed Digital Design
 A Handbook  of Interconnect and Design Practices", John Wiley & Sons, Inc.
2. Todd Westerhoff, "Basic SI and Timing Budgets for common Clock Designs",
 Cadence Design systems, Inc.
3. Syed B. Huq, "Effective Signal Integrity Using IBIS Models", DesingConn 2000.

I appreciate your valuable comments.

Respectfully,

Abe Riazi
ServerWorks



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