[SI-LIST] Clock phase Margin

From: "nasir" <nasir@xxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Tue, 30 Sep 2003 00:22:39 +0800

Can someone explain to me how to calculate the Clock phase Margin in a
high speed Receiver interface?

Nasir 

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References:

[SI-LIST] Re: eye diagram
From: San Miguel, Shane

[SI-LIST] Clock phase Margin

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