[SI-LIST] Re: Clock Uncertainty

>   a) Cycle to cycle jitter, derived from source clock generator,
> typically
> +/- 200 ps.
>   b) Clock skew due to distribution, typically +/- 200ps (driver skew
> + PCB
> trace and loading effects).
>   c) Clock noise, highly dependent upon layout specifics, typically
> estimated at +/- 400ps.
>   d) Duty cycle, typically +/- 5%, which affects DDR cycle time.
=20
I take it that a) represents the jitter at the clock generator's output
pins, and c) is board crosstalk and noise from there on, right?

200ps for cycle to cycle jitter is "safe" but may be overly
conservative.  You might find that it's really a lot less, or that you
can make it better.

You can control crosstalk, through careful routing.

If noise is +/- 400ps, it gets you both ways.  It could move one clock
+400ps and the other (or the next edge) -400ps.  So we should see
(2*noise) in some of your calculations.

I don't follow the difference between rising and falling edge signals.
Do you mean rising and falling address/data signals?  If so, why would
the clock analysis differ?

If you mean rising and falling clock, again why would it matter?  Or do
you really mean full-cycle vs. half-cycle transfers?

Why cut the jitter in half?  Unless you know it's a linearly
accumulating jitter, it could be just as bad from rising to falling edge
as it is from rising to rising.

Allocating 16% of your cycle time to clock effects isn't so bad.  The
truth is that many designs in the past were at least as bad, people just
didn't take the time to analyze them carefully, if at all.  Or they were
lucky.  And nobody said it was going to be easy to run faster.

Regards,
Andy

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