[SI-LIST] Clock Uncertainty

Hi All,

As bus clock speeds increase, clock uncertainty for traditional synchronous
designs (distributed clock...not source synchronous clocking) begins to eat
up more and more of our timing budget.
I would like some feedback on what others are using in their analysis and
their designs.

Specifically, consider a syncronous memory bus operating at 100MHz, using
DDR memory. Clock uncertainties can be broken down into the following
components:
  a) Cycle to cycle jitter, derived from source clock generator, typically
+/- 200 ps.
  b) Clock skew due to distribution, typically +/- 200ps (driver skew + PCB
trace and loading effects).
  c) Clock noise, highly dependent upon layout specifics, typically
estimated at +/- 400ps.
  d) Duty cycle, typically +/- 5%, which affects DDR cycle time.

Considering DDR data writes at 100MHz, setup time for rising edge signals
has clock uncertainty of jitter+skew+noise = 800ps, which is 16% of
half-cycle budget. For falling edge signals, uncertainty becomes
(jitter/2)+skew+noise+duty_cycle = 1.2ns, which is 24% of budget!

Hold times have clock uncertainty of skew+noise = 600ps, which is slightly
lower.

Extending this to faster data rates (such as 166MHz DDR), these
uncertainties become a huge part of the timing budget.

Comments?
AAron

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