[SI-LIST] Re: Clock Jitter - PDN Impedance Profile

Greg,
In addition to all the advice you've got so far, you can investigate this 
problem by measuring the frequency characteristic of the power distribution 
impedance seen by the clock generator IC, driver, and receiver circuits, and 
compare the magnitude and frequency of resonance peaks between  your board and 
the original proto board and also with your clock frequency.  Contact me if you 
have questions about how to measure the freq. char. of PDN.

Cosmin Iorga, Ph.D.
NoiseCoupling.com
http://www.noisecoupling.com







________________________________
From: "Pietz, Greg P" <greg.pietz@xxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, June 30, 2009 6:55:10 AM
Subject: [SI-LIST] Clock Jitter

We have a board design using PCIe.  The PCIe reference clock for each ASIC 
comes from a clock generator IC.  On initial proto boards, build in the USA, 
the clock jitter was about 78ps or less on all boards tested.  We then had 
boards built overseas and are seeing jitter of 90 to 100ps.  This is greater 
then the spec allows and is causing problems with the link.  I did a TDR of the 
clock traces and they are 100 ohms differential.

For two of the board vendors I was able to make some changes to the design to 
get their jitter in spec.  For the third vendor I have been unable to fix the 
jitter problem.

The board stackup is the standard 6 layer design.  The clocks all reference the 
ground plan.
My question is what can a board vendor do to increase clock jitter.

Thanks,
Greg



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