[SI-LIST] Re: Clock Jitter

Jitter is any variation in the time the signal ( pair ) crosses the 
switching threshold.  It has both random and deterministic sources.
Richard Jungert wrote:
> I don't quite get how small changes in board construction can increase 
> jitter.
> If one isolates the oscillator with good power filters and good ground 
> plane splits then how can the noise get in to modulate the oscillator?
>  
> Jitter is all about randomness right?
>  
> Richard Jungert
>
>  
> > Date: Tue, 30 Jun 2009 16:48:00 +0200
> > From: hermann.ruckerbauer@xxxxxxxxxxxxx
> > To: r_jungert@xxxxxxxxxxx
> > CC: greg.pietz@xxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Clock Jitter
> >
> > Content-Type: text/plain; charset=ISO-8859-1
> > Content-Transfer-Encoding: quoted-printable
> > Hi,
> >
> > although some explantions came back I guess the orignal question was not
> > really answered. What can be the difference in PCB manufacuring to
> > increase jitter ?
> >
> > I think the hint to power/ground noise is quite good. We have seen, that
> > the Copper thickness is varying quite a bit with different vendors, what
> > might cause a difference in power noise between the different boards.
> > But what would worry me is, that such a small change should change your
> > design from pass to fail. If your design is that critical it is not
> > stable enough for HVM (high volumen manufacturing). In a volume
> > production you will see a certain distribution of the Power plane
> > thickness what could be a big problem for sutch a design.
> >
> > As you measured your impdance and confirmed the same value I would not
> > really expect the issue to come from the dielectric properties. If they
> > would change too much this would influence er and therefore the
> > impedance. Overall I would not really see this to cause a bigger change
> > for the Jitter (but is 20ps really a bigger change ??)
> >
> > What I would see as another possiblilty is e.g. the size of Anti-pads.
> > If there are some Anti-pads along the current return they might even
> > create a cut in the Ground plane when the PCB manufacterer does some
> > overetch. Basically it might be possible to see such things in the TDR,
> > but maybe the effect is big enough to shift a reflection a bit, but not
> > easily see it as difference in the TDR.
> >
> > regards
> >
> > Hermann
> >
> >
> >
> >
> > EKH - EyeKnowHow
> > Hermann Ruckerbauer
> > www.eyeknowhow.de
> > hermann.ruckerbauer@xxxxxxxxxxxxx
> > Veilchenstrasse 1
> > 94554 Moos
> > Tel.: +49 (0)9938 / 902083
> > Mobile: +49 (0)176 / 787 787 77
> > Fax: +49 (0)721 / 151 258 230
> >
> >
> >
> > Richard Jungert schrieb:
> > > Greg.
> > >
> > > =20
> > >
> > > Its more than likely power noise or noise from the ground plane 
> getting=
> > into the oscillator.=20
> > >
> > > You might need to put a moat in the ground plane and power plane 
> on the=
> > oscillator to cut the jitter cuz noise can sneak in any connection 
> thru =
> > the ground or the power.=20
> > >
> > > =20
> > >
> > > I was suprized how much the noise on the ground can sneak into an 
> oscil=
> > lator when we had to fix this probklem type years ago on a video 
> graphics=
> > board. Originally I thought it was power noise but turned out to be 
> grou=
> > nd noise causing the problem.=20
> > >
> > > =20
> > >
> > > Are the any splits in your ground plane around the oscillator? Is 
> the o=
> > scillator in the middle of the board is another issue that can make 
> it wo=
> > rse.
> > >
> > > =20
> > >
> > > If you free run the oscillator with a battery how much jitter is 
> presen=
> > t? Getting the jitter within spec is hard work! Try free running it 
> by i=
> > tself totally away from the circuit board to see what stand alone 
> best ca=
> > se jitter can be.=20
> > >
> > > =20
> > >
> > > Richard Jungert
> > >
> > > =20
> > >
> > >
> > > =20
> > > =20
> > >> Subject: [SI-LIST] Re: Clock Jitter
> > >> Date: Tue, 30 Jun 2009 10:06:28 -0400
> > >> From: mrose@xxxxxxxxxxxx
> > >> To: greg.pietz@xxxxxx; si-list@xxxxxxxxxxxxx
> > >>
> > >> Greg,
> > >>
> > >> Is the additional jitter DJ or RJ? If it's uncorrelated, you 
> could loo=
> > k
> > >> at power noise. If it's DJ, you may want to look at the relative
> > >> magnitude of the impedance discontinuities (traces, vias, 
> connectors).=
> >
> > >> Did you check trace coupons? Also, you might check if there is any
> > >> additional duty cycle distortion from the oscillator.
> > >>
> > >> Good luck
> > >>
> > >> -----Original Message-----
> > >> From: si-list-bounce@xxxxxxxxxxxxx 
> [mailto:si-list-bounce@xxxxxxxxxxxx=
> > g]
> > >> On Behalf Of Pietz, Greg P
> > >> Sent: Tuesday, June 30, 2009 9:55 AM
> > >> To: si-list@xxxxxxxxxxxxx
> > >> Subject: [SI-LIST] Clock Jitter
> > >>
> > >> We have a board design using PCIe. The PCIe reference clock for each
> > >> ASIC comes from a clock generator IC. On initial proto boards, 
> build i=
> > n
> > >> the USA, the clock jitter was about 78ps or less on all boards 
> tested.=
> >
> > >> We then had boards built overseas and are seeing jitter of 90 to 
> 100ps=
> > =2E
> > >> This is greater then the spec allows and is causing problems with the
> > >> link. I did a TDR of the clock traces and they are 100 ohms
> > >> differential.
> > >>
> > >> For two of the board vendors I was able to make some changes to the
> > >> design to get their jitter in spec. For the third vendor I have been
> > >> unable to fix the jitter problem.
> > >>
> > >> The board stackup is the standard 6 layer design. The clocks all
> > >> reference the ground plan.
> > >> My question is what can a board vendor do to increase clock jitter.
> > >>
> > >> Thanks,
> > >> Greg
> > >>
> > >>
> > >>
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