[SI-LIST] Re: Clock Jitter

Greg.

 

Its more than likely power noise or noise from the ground plane getting into 
the oscillator. 

You might need to put a moat in the ground plane and power plane on the 
oscillator to cut the jitter cuz noise can sneak in any connection thru the 
ground or the power. 

 

I was suprized how much the noise on the ground can sneak into an oscillator 
when we had to fix this probklem type years ago on a video graphics board. 
Originally I thought it was power noise but turned out to be ground noise 
causing the problem. 

 

Are the any splits in your ground plane around the oscillator? Is the 
oscillator in the middle of the board is another issue that can make it worse.

 

If you free run the oscillator with a battery how much jitter is present?  
Getting the jitter within spec is hard work! Try free running it by itself 
totally away from the circuit board to see what stand alone best case jitter 
can be. 

 

Richard Jungert

 


 
> Subject: [SI-LIST] Re: Clock Jitter
> Date: Tue, 30 Jun 2009 10:06:28 -0400
> From: mrose@xxxxxxxxxxxx
> To: greg.pietz@xxxxxx; si-list@xxxxxxxxxxxxx
> 
> Greg,
> 
> Is the additional jitter DJ or RJ? If it's uncorrelated, you could look
> at power noise. If it's DJ, you may want to look at the relative
> magnitude of the impedance discontinuities (traces, vias, connectors).
> Did you check trace coupons? Also, you might check if there is any
> additional duty cycle distortion from the oscillator.
> 
> Good luck
> 
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Pietz, Greg P
> Sent: Tuesday, June 30, 2009 9:55 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Clock Jitter
> 
> We have a board design using PCIe. The PCIe reference clock for each
> ASIC comes from a clock generator IC. On initial proto boards, build in
> the USA, the clock jitter was about 78ps or less on all boards tested.
> We then had boards built overseas and are seeing jitter of 90 to 100ps.
> This is greater then the spec allows and is causing problems with the
> link. I did a TDR of the clock traces and they are 100 ohms
> differential.
> 
> For two of the board vendors I was able to make some changes to the
> design to get their jitter in spec. For the third vendor I have been
> unable to fix the jitter problem.
> 
> The board stackup is the standard 6 layer design. The clocks all
> reference the ground plan.
> My question is what can a board vendor do to increase clock jitter.
> 
> Thanks,
> Greg
> 
> 
> 
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