[SI-LIST] Re: Clock Jitter

This is a great reference for noise sources in oscillators. He talks about 
phase noise, noise bandwidth, quadrature noise and non-linear effects in FET 
amplifiers etc etc. 
 
Phase noise in signal sources
 By W. P. Robins

 

Richard Jungert

 

 

 

 


 
> From: al@xxxxxxxxxxxxx
> To: r_jungert@xxxxxxxxxxx; eddyvk@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Clock Jitter
> Date: Mon, 6 Jul 2009 11:49:02 -0700
> 
> Typical fundamental or 3rd overtone oscillators, in my experience, push the
> noise floor measurement limitations of either sampling or real time
> oscilloscope (<1ps RMS) solutions. Accordingly, I think it makes some
> sense to make Spectrum Analysis measurements of the oscillator of both the
> older boards and the newer suspected problem board first, before examining
> the synthesizer output. The Agilent folks have some really good solutions
> for these measurements, and we have had good success renting good spectrum
> analyzers. Most oscillators are not very tolerant of external noise, and
> easily translate extrinsic noise into time domain jitter though a host of
> amplitude to timing jitter conversions. It is also informative to check
> the rise/fall time and pulse fidelity of the oscillator and verify there
> isn?t a lot of ringing or another apparent SI problem. A slower rise/fall
> can translate into a bit more jitter (use a FET differential plug in, high
> input impedance on output/ground differentially) PDN oscillations, crosstalk
> coupling, etc., will show up as spurious responses and the overlay will
> possibly point to issues between the boards. The phase noise spectrum,
> offset from the carrier relates to the time domain RJ, and the peaks or
> spurs relates to either periodic jitter or some deterministic jitter. Be
> careful that crosstalk can easily be confused with simple RJ in both the
> scopes and the spectrum analyzer. It helps a bit to be able to turn other
> digital aggressors off/on, and provide a pristine non-switching power supply
> externally if possible.
> 
> Moving on to the synthesizer... since the synthesizer multiplies the
> oscillator output (Xfreq multiplies jitter up), and probably generates
> considerable intrinsic RJ, due to relatively noisy internal VCO (and some
> charge pump leakage, or periodic jitter) you can then use both the spectrum
> analyzer AND a suitable scope solution which has RJ-DJ extraction to further
> analyze the differences between the boards. 
> 
> The spectrum analyzer will show phase noise and will additionally give you
> an idea for the PLL loop dynamics, so that you can also check for the proper
> external loop filter being applied (check for peaking in the loop response
> between the boards). A lot of peaking in the loop response suggests the
> loop isn?t set right. Higher levels of phase noise suggest larger RJ, and
> more peaks suggest some form of deterministic jitter.
> 
> Also, an overlay of full impedance profiles, including all pads and
> transitions would be useful in comparing the boards.
> 
> 
> 
> 
> Alfred P. Neves <*)))))><{ 
> 
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Richard Jungert
> Sent: Sunday, July 05, 2009 12:48 PM
> To: eddyvk@xxxxxxxxx; si list freelist
> Subject: [SI-LIST] Re: Clock Jitter
> 
> It is equally important to place the clock oscillator out near the edge of
> the board and do proper grounding with ground plane splits or moats. If the
> clock is placed in the middle of the PC board then it is real susceptable to
> modulation from ground noise when there are no ground plane cuts or moats.
> Use a ground plane moat with all the support circuits for the oscillator and
> you have a winner. 
> 
> 
> 
> What is the Jitter with a free running circuit in its most simplest
> configuration and not connected to any other circuits other than a simple
> resistive load? This is a good place to start when trying to specify jitter
> performance. 
> 
> 
> 
> I am creating these messages because of my real world experience in reducing
> clock jitter on 5 old video and digital radio projects to almost no jitter.
> On one, we reduced phase jitter to <0.1% with a few simple ideas. In video
> and radio circuits the clock jitter and phase noise have to be minumal to
> get good system performance. 
> 
> 
> 
> Richard Jungert
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> > Date: Sun, 5 Jul 2009 09:47:57 -0700
> > From: eddyvk@xxxxxxxxx
> > Subject: [SI-LIST] Re: Clock Jitter
> > To: si-list@xxxxxxxxxxxxx
> > 
> > 
> > The clock generator IC is most likely a synthesizer that multiplies the
> frequency up from a crystal reference. These synthesizers can be very
> sensitive to noise frequencies near their loop bandwidth, usually in the
> region 500KHz~5MHz. Most RF chokes have trouble stopping these relatively
> low frequencies and I find an ordinary resistor of a few ohms to work better
> sometimes.
> > The synthesizer can also be very sensitive to the noise it creates itself
> on its power lines. Therefor power supply decoupling is VERY important. Move
> the decoupling capacitor 1mm further away from the clock chip and the jitter
> may go up with more than 20ps. Because of the sensitivity to decoupling
> 'quality' I agree with Jose below that a simple change of capacitor
> manufacturer and/or capacitor dielectric can cause the jitter change that
> you see. CM's are always seeking to lower cost....
> > 
> > The jitter numbers you are speaking of are most likely PkPk unit of the
> Period Jitter kind. PkPk numbers are not very exact. You can do one
> measurement and get for example 80ps PkPk. Then you do another measurement
> with the same setup and you get 90ps. If 90~100ps is already causing real
> trouble then a nominal 78ps is too close for comfort. You may be able to
> clean up the environment around the current chip such that it improves or
> else chose another clock chip generator.
> > 
> > You mentioned you were able to fix some PCB's. What did you do to fix
> them? Possibly the root cause of what caused the jitter to go up is in the
> area of what you did to bring it back down. 
> > 
> > Good luck fixing your jitter problem!
> > 
> > Eddy van Keulen
> > Fremont CA, USA
> > 
> > 
> > 
> > --- On Tue, 6/30/09, Moreira, Jose <jose.moreira@xxxxxxxxxx> wrote:
> > >
> > > From: Moreira, Jose <jose.moreira@xxxxxxxxxx>
> > > Subject: [SI-LIST] Re: Clock Jitter
> > > To: "si list freelist" <si-list@xxxxxxxxxxxxx>
> > > Date: Tuesday, June 30, 2009, 8:16 AM
> > > 
> > > Why are you assuming that the problem is with the bare
> > > PCB?
> > > 
> > > Is the Bill of Material exactly the same as your reference
> > > board. i.e. the values part numbers and vendors of all used
> > > parts (IC's, Cap's, etc.) are the same from the US and Far
> > > East manufacturers? You would not be the first to have a
> > > part changed to a different vendor (usually much cheaper)
> > > that impacts your design.
> > > 
> > > 
> > > 
> > > 
> > > 
> > > 
> > > 
> > > -----Original Message-----
> > > From: si-list-bounce@xxxxxxxxxxxxx
> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > > On Behalf Of Richard Jungert
> > > Sent: Tuesday, June 30, 2009 5:01 PM
> > > To: hermann.ruckerbauer@xxxxxxxxxxxxx;
> > > greg pietz; si list freelist; steve weir
> > > Subject: [SI-LIST] Re: Clock Jitter
> > > 
> > > I don't quite get how small changes in board construction
> > > can increase jitter. 
> > > 
> > > If one isolates the oscillator with good power filters and
> > > good ground plane splits then how can the noise get in to
> > > modulate the oscillator? 
> > > 
> > > 
> > > 
> > > Jitter is all about randomness right? 
> > > 
> > > 
> > > 
> > > Richard Jungert
> > > 
> > > 
> > > 
> > > > Date: Tue, 30 Jun 2009 16:48:00 +0200
> > > > From: hermann.ruckerbauer@xxxxxxxxxxxxx
> > > > To: r_jungert@xxxxxxxxxxx
> > > > CC: greg.pietz@xxxxxx;
> > > si-list@xxxxxxxxxxxxx
> > > > Subject: [SI-LIST] Re: Clock Jitter
> > > > 
> > > > Content-Type: text/plain; charset=ISO-8859-1
> > > > Content-Transfer-Encoding: quoted-printable Hi,
> > > > 
> > > > although some explantions came back I guess the
> > > orignal question was 
> > > > not really answered. What can be the difference in PCB
> > > manufacuring to 
> > > > increase jitter ?
> > > > 
> > > > I think the hint to power/ground noise is quite good.
> > > We have seen, 
> > > > that the Copper thickness is varying quite a bit with
> > > different 
> > > > vendors, what might cause a difference in power noise
> > > between the different boards.
> > > > But what would worry me is, that such a small change
> > > should change 
> > > > your design from pass to fail. If your design is that
> > > critical it is 
> > > > not stable enough for HVM (high volumen
> > > manufacturing). In a volume 
> > > > production you will see a certain distribution of the
> > > Power plane 
> > > > thickness what could be a big problem for sutch a
> > > design.
> > > > 
> > > > As you measured your impdance and confirmed the same
> > > value I would not 
> > > > really expect the issue to come from the dielectric
> > > properties. If 
> > > > they would change too much this would influence er and
> > > therefore the 
> > > > impedance. Overall I would not really see this to
> > > cause a bigger 
> > > > change for the Jitter (but is 20ps really a bigger
> > > change ??)
> > > > 
> > > > What I would see as another possiblilty is e.g. the
> > > size of Anti-pads.
> > > > If there are some Anti-pads along the current return
> > > they might even 
> > > > create a cut in the Ground plane when the PCB
> > > manufacterer does some 
> > > > overetch. Basically it might be possible to see such
> > > things in the 
> > > > TDR, but maybe the effect is big enough to shift a
> > > reflection a bit, 
> > > > but not easily see it as difference in the TDR.
> > > > 
> > > > regards
> > > > 
> > > > Hermann
> > > > 
> > > > 
> > > > 
> > > > 
> > > > EKH - EyeKnowHow
> > > > Hermann Ruckerbauer
> > > > www.eyeknowhow.de
> > > > hermann.ruckerbauer@xxxxxxxxxxxxx
> > > > Veilchenstrasse 1
> > > > 94554 Moos
> > > > Tel.: +49 (0)9938 / 902083
> > > > Mobile: +49 (0)176 / 787 787 77
> > > > Fax: +49 (0)721 / 151 258 230
> > > > 
> > > > 
> > > > 
> > > > Richard Jungert schrieb:
> > > > > Greg.
> > > > >
> > > > > 
> > > > >
> > > > > Its more than likely power noise or noise from
> > > the ground plane getting> into the oscillator. 
> > > > >
> > > > > You might need to put a moat in the ground plane
> > > and power plane on the> oscillator to cut the jitter cuz
> > > noise can sneak in any connection thru > the ground or
> > > the power. 
> > > > >
> > > > > 
> > > > >
> > > > > I was suprized how much the noise on the ground
> > > can sneak into an oscil> lator when we had to fix this
> > > probklem type years ago on a video graphics> board.
> > > Originally I thought it was power noise but turned out to be
> > > grou> nd noise causing the problem. 
> > > > >
> > > > > 
> > > > >
> > > > > Are the any splits in your ground plane around
> > > the oscillator? Is the o> scillator in the middle of the
> > > board is another issue that can make it wo> rse.
> > > > >
> > > > > 
> > > > >
> > > > > If you free run the oscillator with a battery how
> > > much jitter is presen> t? Getting the jitter within spec
> > > is hard work! Try free running it by i> tself totally
> > > away from the circuit board to see what stand alone best
> > > ca> se jitter can be. 
> > > > >
> > > > > 
> > > > >
> > > > > Richard Jungert
> > > > >
> > > > > 
> > > > >
> > > > >
> > > > > 
> > > > > 
> > > > >> Subject: [SI-LIST] Re: Clock Jitter
> > > > >> Date: Tue, 30 Jun 2009 10:06:28 -0400
> > > > >> From: mrose@xxxxxxxxxxxx
> > > > >> To: greg.pietz@xxxxxx;
> > > si-list@xxxxxxxxxxxxx
> > > > >>
> > > > >> Greg,
> > > > >>
> > > > >> Is the additional jitter DJ or RJ? If it's
> > > uncorrelated, you could 
> > > > >> loo> k at power noise. If it's DJ, you may
> > > want to look at the 
> > > > >> relative magnitude of the impedance
> > > discontinuities (traces, vias, 
> > > > >> connectors).> Did you check trace coupons?
> > > Also, you might check if 
> > > > >> there is any additional duty cycle distortion
> > > from the oscillator.
> > > > >>
> > > > >> Good luck
> > > > >>
> > > > >> -----Original Message-----
> > > > >> From: si-list-bounce@xxxxxxxxxxxxx
> > > 
> > > > >> [mailto:si-list-bounce@xxxxxxxxxxxx>
> > > g] On Behalf Of Pietz, Greg P
> > > > >> Sent: Tuesday, June 30, 2009 9:55 AM
> > > > >> To: si-list@xxxxxxxxxxxxx
> > > > >> Subject: [SI-LIST] Clock Jitter
> > > > >>
> > > > >> We have a board design using PCIe. The PCIe
> > > reference clock for 
> > > > >> each ASIC comes from a clock generator IC. On
> > > initial proto boards, 
> > > > >> build i> n the USA, the clock jitter was
> > > about 78ps or less on all 
> > > > >> boards tested.> We then had boards built
> > > overseas and are seeing jitter of 90 to 100ps> .
> > > > >> This is greater then the spec allows and is
> > > causing problems with 
> > > > >> the link. I did a TDR of the clock traces and
> > > they are 100 ohms 
> > > > >> differential.
> > > > >>
> > > > >> For two of the board vendors I was able to
> > > make some changes to the 
> > > > >> design to get their jitter in spec. For the
> > > third vendor I have 
> > > > >> been unable to fix the jitter problem.
> > > > >>
> > > > >> The board stackup is the standard 6 layer
> > > design. The clocks all 
> > > > >> reference the ground plan.
> > > > >> My question is what can a board vendor do to
> > > increase clock jitter.
> > > > >>
> > > > >> Thanks,
> > > > >> Greg
> > > > >>
> > > > >>
> > > > >>
> > > > >>
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