[SI-LIST] Re: Cascading PLL

  • From: timoceous <timoceous@xxxxxxxxx>
  • To: a.ingraham@xxxxxxxx, si <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 13 May 2004 11:39:05 -0700 (PDT)

Hi all,

  Thanks for the kind and insightful reply by
Mickael Poimboeuf and Andrew Ingraham.

     I will do some more experiments and let you guys
know how it went.

Regards,

Tim


--- "Ingraham, Andrew" <a.ingraham@xxxxxxxx> wrote:
> I like Michael Poimboeuf's answer.  Good reply.
> 
> To elaborate a bit more on the choice between wider
> or narrower in your
> second PLL...
> 
> If you are very concerned about keeping the second
> PLL from losing lock,
> perhaps it should be wider than the first PLL.  That
> way it has a better
> chance of tracking jitter and phase or frequency
> changes that come down the
> line from the slower first PLL.  If you are paranoid
> about cascading two
> identical PLLs, this might be your better choice.
> 
> On the other hand, it is not necessarily bad to
> follow a PLL with one that
> is narrower than the first.  PLLs are often used to
> clean up noisy (jittery)
> signal sources.  In this application a narrowband
> PLL is very desirable.
> You just need to have a handle on how much
> worst-case jitter might be coming
> from the first PLL, and do an analysis that the
> second PLL doesn't lose lock
> from it, and that your system can tolerate the phase
> error due to the fact
> that the second PLL is averaging the phase and not
> tracking it.
> 
> Regards,
> Andy
> 
> >    I have a question on the one PLL driving
> another
> > PLL.  I know that if both PLL has the same
> bandwidth
> > it is not a good idea.  So my questions is what
> should
> > the 1st PLL bandwidth should be, should be be
> narrow
> > band and the 2nd PLL to be a wideband PLL?  Or is
> it
> > the
> > other way around?  Is there any articles
> discussion
> > this
> > issue.  Thanks in advance.
> 
> 
>
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