[SI-LIST] Re: Capacitor surge current

  • From: Mike Brown <bmgman@xxxxxxxxxx>
  • To: dimiter.popoff@xxxxxxxxxxx
  • Date: Thu, 11 Mar 2004 23:25:15 -0600

It seems to me that the capacitor explosion phenomenon is likely a peak 
power problem.

The stored energy is Cv^2/2.  That's also the energy dissipated in the 
process of charging the cap.  Where does this dissipation happen?  In 
the Z of the charging supply, and in the ESR of the cap.  If the ESR is 
large compared to the supply impedance, the dissipation is mainly in the 
cap.  The power is E/t, and t can be pretty small.

There's an I^2*t limit on the component - probably unpublished - that 
lets the smoke out if it is exceeded.

We were popping inrush limiting FETs a while back, due to an unannounced 
change (a so-called process improvement, putting a smaller die in the 
package, raising the thermal resistance and decreasing the thermal 
capacity) in the  I^2*t rating of the FET we were using.   I see no 
fundamental reason why the cap shouldn't pop due to similar overstress.

Mike

Dimiter Popoff wrote:

>  Quite recently I had a related problem. I designed for a guy a device
> which included a +/- 100V , apr. 10W DC-DC convertor. No rocket science,
> things went just as expected.
>  I had put a number of 1206 ceramic caps (like a stripe under the 
> electrolythic
> one), which was 100% overkill but I just repeated what I usually did
> when noise is a real issue (like 14 bit precision @ 10 MSPS, which was
> worlds away from this particular case).
>  The 1206 caps were rated at 200V. Well, after a few days of usage the first 
> of
> them exploded. Another few days later the next one; and then another one...
> The common was that they did it on power on.
>  A closer look revealed I had messed up the soft start circuit and the
> convertor would start abruptly; then, the coil was 30W capable (I know
> this from other designs) and the secondary was really low impedance.
> Frankly, I would not have believed this were possible if I had been told
> that before - but the inrush current really blasted those caps (which
> we tested to truly sustain 200V DC over time and which never saw more
> than 100V in the actual circuit, no peaks etc.).
>  Has anyone had similar experience? I cannot think of another reason
> why the 1206 ceramic caps would explode upon power up without any
> overvoltage spikes, but then I did not really measure/record the
> inrush currents I suspect, so the issue - while practically solved - is
> not quite closed for me.
> 
> Dimiter
> 
> -----------------------------------------------------------------
> Dimiter Popoff                                    ++359/2/9923340
> Transgalactic Instruments, Gourko Str. 25 b, 1000 Sofia, Bulgaria
> http://tgi.cit.bg       tgi@xxxxxx     dimiter.popoff@xxxxxxxxxxx
> -----------------------------------------------------------------
> 
> 
> 
>>To: si-list@xxxxxxxxxxxxx
>>From: Hal Murray <hmurray@xxxxxxxxxxxxxxx>
>>Subject: [SI-LIST] Re: Capacitor surge current 
>>Date: Thu, 11 Mar 2004 09:10:44 -0800
>>
>>
>>Suppose I was trying to design a good/safe circuit using large ceramic caps.  
>>Is there anything in the data sheet that tells me how much current they can 
>>take?
>>
>>Most data sheets for electrolytic caps have ripple current specs.  I don't 
>>remember seeing anything like that for ceramic caps.  I just scanned a few 
>>data sheets that I had handy.  I didn't see anything, but maybe other data 
>>sheets are better.
>>
>>What sort of low duty cycle peak currents are reasonable?  The particular 
>>case that started this discussion seems to be due to a turn-on surge.  I'm 
>>surprised that an occasional event like that would harm a capacitor.  How 
>>would I calculate a safe rise time?  Or is that even the right question?
> 
> 
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