[SI-LIST] Re: Capacitance and excess propagation time of via

George,

Thank you for your fruitful comment. Your comment is very useful for 
us. We will try to verify the inductance variation as you mentioned.

Sogo Hsu, Ph. D.
Foxconn

--- In si-list@xxxxxxxxxxxxxxx, "George Tang" <gtang@xxxx> wrote:
> Sogo,
> 
> There are several factors that can cause this phenomenon.
> 
> 1. In case I, you have 2 vias, (vias A &B).  In case II, you have 
4 vias (C,
> D, E, & F).  As signal propagates through vias A & B, there is no
> designed-in return path, so the via inductance is large.  But vias 
D & E
> forms a small loop (lower inductance), so faster propagation 
results.
> Propagation delay is determined by
> 1/sqrt(LC).  L is different for each via.
> 
> 2. If the rising edge is sharp (high freq. components), the 
capacitive
> coupling between vias D & E may allow the signal to propagate 
through.
> 
> Other factors like trace length, board thickness, via diameter, 
all play a
> role, but for the given info, this is the simple response.
> 
> George
> 
> 
> 
> -----Original Message-----
> From: si-list-bounce@xxxx
> [mailto:si-list-bounce@xxxx]On Behalf Of Sogo Hsu
> Sent: Tuesday, March 23, 2004 4:30 PM
> To: si-list@xxxx
> Subject: [SI-LIST] Capacitance and excess propagation time of via
> 
> 
> Hi, Gurus,
> 
> Sorry to my ambiguity ASCII code in the previous message. I try to
> send the mail again.
> 
> The capacitance of via was usually estimated by the formula as 
below
> 
> C =3D 1.41 epsilon_r * T * D1 / (D2 =A1VD1).
> 
> The definition of T is the total thickness of PCB by refering Dr.
> Johnson's black magic bible. It seems like that the formula implied
> the capacitance is formed by plate capacitor where the area is
> constructed by the conducted via body and space is (D2- D1)/2. Is 
it
> reasonable for a multi-layer PCB structure? In my opinion, the only
> effective thickness is the total thickness of pwr/gnd plane which
> the via passing through. Therefore, I think the estimation of
> capacitance is over-estimate. The full wave analysis results, such
> as HFSS, also presented the characteristic of via is inductive
> dominantly. That is said, via did not have such large capacitance
> inherently.
> 
> Besides, we also ! tried to estimate the excess propagation time
> when the signal traveling through via. Two cases are under
> onsideration as below. The test vehicle is a 4-layer PCB.
> 
> Case I
> (TOP) ====                                             ======
>          ||                                           ||
>          ||                                           ||
>          ===============================================
> (Bottom)
> 
> Case II
> (Top)
>      ====               ===============               ======
>         ||              ||           ||               ||
>         ||              ||           ||               ||
>         =================            ==================
> (Bottom)
> 
> Case I consists of two vias for layer change and Case II has four
> vias. The total trace length is same to each other. The propagation
> time was measured by TDT. The excess propagation time caused by via
> can be obtained by subtracting with the propagation delay of
> microstrip in equal length. The excess propagation time per unit 
via
> for Case II is obviously faster in a factor of 60% than Case I as
> well. Does any one meet this phenomenon before? It is suspect that
> is the result of via coupling. I hope any expert can give me a
> reasonable explanation on this phenomenon. Thank you in advance.
> 
> Sogo Hsu, Ph. D.
> Foxconn Electronic
> 
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