[SI-LIST] Capacitance and excess propagation time of via

Hi, Gurus,

Sorry to my ambiguity ASCII code in the previous message. I try to 
send the mail again.

The capacitance of via was usually estimated by the formula as below

C =3D 1.41 epsilon_r * T * D1 / (D2 =A1VD1).

The definition of T is the total thickness of PCB by refering Dr. 
Johnson's black magic bible. It seems like that the formula implied 
the capacitance is formed by plate capacitor where the area is 
constructed by the conducted via body and space is (D2- D1)/2. Is it 
reasonable for a multi-layer PCB structure? In my opinion, the only 
effective thickness is the total thickness of pwr/gnd plane which 
the via passing through. Therefore, I think the estimation of 
capacitance is over-estimate. The full wave analysis results, such 
as HFSS, also presented the characteristic of via is inductive 
dominantly. That is said, via did not have such large capacitance 
inherently.

Besides, we also ! tried to estimate the excess propagation time 
when the signal traveling through via. Two cases are under 
onsideration as below. The test vehicle is a 4-layer PCB.

Case I
(TOP) ====                                             ======
         ||                                           ||
         ||                                           ||
         ===============================================
(Bottom)

Case II
(Top)
     ====               ===============               ======
        ||              ||           ||               ||
        ||              ||           ||               ||
        =================            ==================
(Bottom)

Case I consists of two vias for layer change and Case II has four 
vias. The total trace length is same to each other. The propagation 
time was measured by TDT. The excess propagation time caused by via 
can be obtained by subtracting with the propagation delay of 
microstrip in equal length. The excess propagation time per unit via 
for Case II is obviously faster in a factor of 60% than Case I as 
well. Does any one meet this phenomenon before? It is suspect that 
is the result of via coupling. I hope any expert can give me a 
reasonable explanation on this phenomenon. Thank you in advance.

Sogo Hsu, Ph. D.
Foxconn Electronic

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: