[SI-LIST] Re: Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic

Hi,

Thanks for the responses. I have downloaded an eval SI
tool (thanks to Giancarlo) and simulated my
approximate setup. Some plain ALVC is not doing so
good but other specific models for a TI buffer are
doing OK. The signal is not driving rail-to-rail but
doing  more than adequately for SSTL_18 levels. 

The duty cycle is also coming in better than I
expected.

Thanks,
Jai
--- Faraydon Pakbaz <pakbazf@xxxxxxxxxx> wrote:

> Jai;
> 
> You can create some behavioral model of IO using a
> RLC model. You can then
> modify this passive elements to deliver the current
> and voltage level
> needed and
> test it for various terminations. Let me know if you
> are interested and I
> can send you
> some slides to describe it. They run a lot faster
> than actual encrypted
> SPICE model
> and IBIS. Thanks.
> 
> Regards;
> 
> Faraydon(Don) Pakbaz
> AE/TS Customer Support Engineering
> Email: pakbazf@xxxxxxxxxx
> Voice: (802) 769-5638  Tieline: 446-5638   Fax:
> (802) 769-5722
> 
> 
>                                                     
>                       
>              steve weir                             
>                       
>              <weirsi@xxxxxxxxx                      
>                       
>              m>                                     
>                    To 
>              Sent by:                 
> jswarrier@xxxxxxxxx,                
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>                                                     
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>                                                     
>               Subject 
>              02/22/2006 04:13          [SI-LIST] Re:
> Can we drive 100Mhz   
>              AM                        SSTL_18 with
> standard ALVC  or      
>                                        other 1.8V
> logic                    
>                                                     
>                       
>              Please respond to                      
>                       
>                   weirsi                            
>                       
>                                                     
>                       
>                                                     
>                       
>                                                     
>                       
> 
> 
> 
> 
> Jai, at such a low bit rate, I think a well
> terminated channel should
> work fine.  If you can't simulate, build a small
> test vehicle.
> 
> Steve.
> 
> At 11:38 PM 2/21/2006, Jai Shanker wrote:
> >Hi All,
> >
> >For a low-cost implementation we are looking to
> drive
> >SSTL_18 receivers on our chip with standard 1.8V
> >single -ended logic for a 100Mhz clock.
> >
> >I have usually used LVPECL for this type of
> >application.
> >
> >I checked it should be OK to drive 1.8V levels to
> the
> >SSTL_18 inputs. The remaining question is about the
> >speed / drive performance of the standard logic.
> >
> >Can I use ALVC244 / 245 type of buffers? They have
> ~
> >6mA symmetric current drive.
> >
> >They dont spec any fMAX or Max data rate info.
> There
> >is such info on some TI devices (SN74AVC8T245,
> > >170Mbps @ 1.8V operation) but they spec a load of
> >15pF+ 2K. The ALVC buffer specs its load at
> 30pF+500
> >ohms. So would they be comparable.
> >
> >I have downloaded some IBIS models of the buffers
> but
> >I dont have easy access to any simulation tool.
> >
> >Has anybody done this or anything similar.
> >
> >Thanks for any help,
> >Jai Warrier
> >
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