[SI-LIST] CML versus ECL/PECL

Here is a question to all design experts: I have been wondering for a 
while what the design advantages (or disadvantages) of CML signaling  vs. 
ECL/PECL signaling are. I can think of a few, but I may be wrong, and I'm 
sure there are more considerations:
- both schemes are typically differential, so no advantage here

- I noticed most high-speed drivers use CML; I guess this is because it 
can easily provide double termination (50 Ohm internal pullup at driver 
and 50 Ohm pullup at receiver) which is important for signal integrity at 
10+ Gb/s

- but I guess that combined 25 load means CML is typically more power 
hungry

- ECL/PECL needs a third voltage (Vcc - 2V) for end termination while CML 
can usually be terminated to Vcc. Of course I can use a approx. 150 Ohm 
pulldown to GND for the driver (assuming 3.3V PECL) to get around this, 
and add a series resistor at the driver and bridge termination at the 
receiver, but that makes for a smaller swing - not good.

- CML can driver larger swings, while ECL/PECL is normally restricted to 
standard values (0.4V or 0.8V swing, respectively).

I'm looking forward to more insight on this.

Regards,

Wolfgang


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