[SI-LIST] Re: CML - Current Model Logic

On Monday 15 October 2001 11:23, Neeraj Pendse wrote:
> Hi,
> 
> I have a question about determining return current paths for CML drivers
> and receivers. The termination for both the lines on CML is to VDD, so
> does that mean that for a CML receiver, the current loop is always
> formed by the signal line to the VSS? And the logic level is determined
> by which signal line is carryinbg current to the VSS? But the VSS is
> ideally carrying a constant DC current ... so how does a CML loop look
> in AC?

CML is current-switched between the two differential lines.
Because the current to the negative supply carries no AC
components you can ignore it for AC analysis purposes.

The important current loop is from the rising half, through the reference
plane, to the falling half.  In parallel is the direct coupling between the
two halves.  Net AC current in the reference plane is also zero.

> Long descriptions about CML will be very apprecitated (asking for too
> much?), but pointer to links which explain CML101 and board routing for
> it would be nice too.

Can't help you.  AFAIK there is no actual standard for CML; it's one of
those "everybody seems to be able to make it work" things.

Besides, it's strictly yesterday.  SLVS is the ticket now :-)

-- 
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat.                |
+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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