[SI-LIST] CML - Current Model Logic

Hi,

I have a question about determining return current paths for CML drivers
and receivers. The termination for both the lines on CML is to VDD, so
does that mean that for a CML receiver, the current loop is always
formed by the signal line to the VSS? And the logic level is determined
by which signal line is carryinbg current to the VSS? But the VSS is
ideally carrying a constant DC current ... so how does a CML loop look
in AC?

Long descriptions about CML will be very apprecitated (asking for too
much?), but pointer to links which explain CML101 and board routing for
it would be nice too.

Thanks in advance,

- Neeraj.

National Semiconductor Corporation
2900 Semiconductor Drive, Mail Stop 19-100
Santa Clara, California 95051
http://www.national.com/, MYSE: NSM
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