[SI-LIST] Re: Bypass Capacitances

Hello Aaditya, 
Istvan and Rick gave you good answers . 
 
I want to add that increasing number of decoupling capacitances might cause 
strong PDN system resonance. PDN noise resonance, 
next in tern, causes on-chip signals Jitter resonance. 
We did experiments which demonstrate these effects and described its in a paper 
"SOC-System Jitter Resonance and Its Impact on Common Approach to the PDN 
Impedance", 2008. 
You might see this paper here: 
http://www.seriallite.com/search?output=xml_no_dtd&sortÚte%3AD%3AL%3Ad1&client=www_frontend&proxystylesheet=www_frontend&ie=UTF-8&oe=UTF-8&site=www&q=SOC-system%20Jitter%20resonance
 
If you have troubles to use this link, let me know and I'll send you a paper.  
 
Continuation of this research published recently at Designcon 2012 - "On-chip 
Jitter and System Power Integrity". 
Increasing the decoupling have been a common approach at PCB design for many 
years.  As papers demonstrates, increasing  
number of decoupling capacitors often makes situation even worse. 
 
Regards, 
Iliya Zamek
Semtech Corp.
________________________________
 From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
To: aaditya.kandibanda@xxxxxxxxx 
Cc: si-list@xxxxxxxxxxxxx 
Sent: Sunday, March 11, 2012 9:33 PM
 Subject: [SI-LIST] Re: Bypass Capacitance?
  
Hello Aaditya,

When we consider the entire chain of power distribution, from DC source 
to silicon,
in most designs today we need different valued capacitors.  At low 
frequencies we
start with bulk capacitors with the highest capacitance value, but those 
having
large inductance, we need to add medium and high frequency capacitors on the
board.  As we move into the package, there could be bypass capacitors in the
package, finally the highest frequency bypassing is served by 
capacitance on the
silicon. As we go from DC source to silicon, typically each subsequent 
capacitor
bank has lower capacitance, but also lower inductance as seen from the 
silicon.
At low frequencies all of these capacitances appear in parallel and the 
limit is
really what the DC source can handle.  Others pointed out ESR, and 
either too low
or too high ESR may cause problems, dependent on what the DC source was
designed for.  Also with too much capacitance the DC source may not 
start properly
or not at all.  Beyond these limits on total capacitance, usually more 
is better,
at least electrically, if we do not consider cost and size.  In each 
bank, if you make
the capacitance bigger, you can afford more inductance in the next 
lower-frequency
bank, making that bank easier to implement and more cost effective. The full
design has to balance the entire chain and find a solution, which meets the
electrical requirements and at the same time comes at the lowest cost 
(or size,
or whatever other design constraints you may have).

Regards,

Istvan Novak
Oracle



On 3/11/2012 1:53 AM, Aaditya Kandibanda wrote:
> Hello Everyone,
> I have a doubt on bypass capacitors, will there be any specific limit to
> the capacitance I can use for bypassing? what if my bypass capacitance is
> very large value? will it be okay?
>
> Thank you in advance,
> Aaditya
>
>
>


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