[SI-LIST] Re: Bypass Capacitance?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 11 Mar 2012 04:42:13 -0700
If PDN design could be adequately described in a few paragraphs, people
wouldn't have design failures.
There are now some decent books dedicated to power distribution: Iorga,
Novak, Swaminathan, etc. There are a number of other books that at
least dedicate chapters to it: Bogatin, Johnson, Ritchey, etc. These
are all worth studying.
Steve
On 3/11/2012 12:45 AM, Rick Collins wrote:
> First, let me say that I am no expert in power distribution system
> (PDS) design. I took a class with Lee Ritchey a few years back and
> tried to absorb everything he taught in that class, which PDS was a
> small part of. There were several points he made which stuck with
> me. We'll see how well I remember...
> 1) To be effective, the impedance of the PDS has to be adequately low
> across the frequency spectrum. Using a single value or type of
> capacitance won't give you that in most situations because capacitors
> are capacitive below their resonance and the impedance
> rises. Capacitors are inductive above their frequency of resonance
> and the impedance also rises. Larger values of electrolytic or
> tantalum capacitors are used to get low impedance at lower
> frequencies. Ceramic caps provide low impedance at higher
> frequencies. Using power planes to form capacitors provides low
> impedance across a range of very high frequencies that discrete
> capacitors can't provide.
>
> 2) Discrete capacitors have effective series resistance (ESR), even
> ceramics, which will mitigate the anti-resonance peak in impedance
> created when more than one value/type of capacitor is used. If
> multiple values of ceramic capacitors are used (more than two) the
> peaks are typically well mitigated. The power planes also have some
> effect in this but I seem to recall it was rather complicated with
> lots of ripple at very high frequencies (> 1 GHz), possibly having to
> do with reflections at the edges of the board, standing waves
> perhaps? What I took away from this was to use 1, 10 and 100 nF
> ceramic caps in addition to the power planes and you should be
> good. You don't need TONS of each part. Lee showed us how to
> calculate the requirement, but it was based on knowledge of the
> current spikes of your chips. If you don't know that there is no way
> to actually know what your PDS requirements are. I've never seen
> this data on any of the chips I use...
>
> 3) When good power planes are used, discrete capacitors do not need
> to be extremely close to the chip they are decoupling. In essence
> the distance to the cap creates a "delay" in action while the E field
> propagates to the cap and back to the chip. The capacitance of the
> power plane provides adequate decoupling during this delay
> time. Think of the power plane as a very low impedance transmission
> line. Lee actually constructed a test board and measured the results
> as the decoupling cap was placed up to more than an inch away from
> the chip (maybe as much as three inches?). The difference in voltage
> variation at the chip was small.
>
> I hate to be spouting all this off because I have not had a lot of
> opportunity to verify it. I may have learned some of it wrong. But
> I am sure it will get a good vetting here and I'll find out if I did
> learn any of it wrong.
>
> BTW, in case you haven't figured it out, I highly recommend Lee's
> class at speedingedge.com
>
> Rick
>
>
> At 04:34 AM 3/11/2012, Aaditya Kandibanda wrote:
>> Hello Rick, thank you very much, I am somewhat confused about the
>> ground plane and power plane capacitance which is formed because of
>> stack up, what is its importance?
>>
>> On Sat, Mar 10, 2012 at 11:22 PM, Rick Collins
>> <<mailto:gnuarm.2006@xxxxxxxxx>gnuarm.2006@xxxxxxxxx> wrote:
>> I don't think it can hurt the devices you are trying to supply power
>> to, but some voltage regulators can be sensitive to low effective
>> series resistance (ESR) capacitors, like ceramic caps. If you
>> provide too many of the low ESR caps the total capacitance can
>> destabilize the regulator to the point of oscillations. If this is a
>> problem, they should tell you the upper limit of capacitance to use.
>> Rick
>> At 03:53 AM 3/11/2012, Aaditya Kandibanda wrote:
>>> Hello Everyone,
>>> I have a doubt on bypass capacitors, will there be any specific limit to
>>> the capacitance I can use for bypassing? what if my bypass capacitance is
>>> very large value? will it be okay?
>>>
>>> Thank you in advance,
>>> Aaditya
>>>
>>>
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