[SI-LIST] Re: Bus contention between FPGA and ZBT
- From: "Lynne D. Green" <lgreen22@xxxxxxxxxxxxxx>
- To: <a.ingraham@xxxxxxxx>, "'si-list'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 20 Apr 2007 11:03:31 -0700
Any simulator that lets you set multiple sources active can do this. This
includes all "flavors" of SPICE, VHDL-AMS & Verilog-AMS, as well as some of
the SI tools. The only "physics" requirement is that the sources not be
shorted together; they must be separated by a transmission line or other
element.
If the sources are separated by a transmission line, they might need to be
at the same initial voltage for DC convergence at the beginning of the
simulation.
Best regards,
Lynne
"IBIS training when you need it, where you need it."
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Andrew Ingraham
Sent: Thursday, April 19, 2007 7:48 AM
To: si-list
Subject: [SI-LIST] Re: Bus contention between FPGA and ZBT
> Is there a simulator that can have data traveling in both directions
> at the same time ?
Um, SPICE?
What I can't understand about new-and-improved simulators, is the lost
capabilities that we have enjoyed for decades.
Andy
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- References:
- [SI-LIST] Re: Bus contention between FPGA and ZBT
- From: Andrew Ingraham
Other related posts:
- » [SI-LIST] Bus contention between FPGA and ZBT
- » [SI-LIST] Re: Bus contention between FPGA and ZBT
- » [SI-LIST] Re: Bus contention between FPGA and ZBT
- » [SI-LIST] Re: Bus contention between FPGA and ZBT
- » [SI-LIST] Re: Bus contention between FPGA and ZBT
- [SI-LIST] Re: Bus contention between FPGA and ZBT
- From: Andrew Ingraham