[SI-LIST] Re: Best PDS impedance for package damping
- From: "John Lipsius" <jlipsius@xxxxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 13 Feb 2004 14:26:28 -0800
All,
For the pcb end of things, both the decap ESL and ESR are critical=20
of course. Whatever your philosophy, the ESL variation will shift=20
the resonance and change your Q, and the ESR will mainly raise or=20
lower the peak of the "V". =20
Therefore, can anyone talk about the quality of the data from vendors'=20
free tools that use a simple GUI to provide ESR, ESL and f response?=20
(Which will always be changed by the mounting L.)
For example, spitan and spicap from AVX.=20
Thanks,
John
> -----Original Message-----
> From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
> Sent: Friday, February 13, 2004 12:38 PM
> To: steve weir
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Best PDS impedance for package damping
>=20
>=20
> Steve - I completely agree that IC manufacturers should tell=20
> the board=20
> integrators about the inductance, capacitance and the transient=20
> current properties of their product. Unfortunately, they usually=20
> don't know. It is easy to get capacitance information on a few gates=20
> or inductance information on a few pins or vias. But it is difficult=20
> to obtain the aggregate (equivalent) inductance and capacitance that=20
> appears to the PCB PDS. Transient current is often more difficult=20
> than inductance or capacitance and depends on the code that=20
> is running=20
> at the time.
>=20
> Another way to get this information is to measure it yourself. By=20
> mounting a processor or major ASIC on a bare fab, it is not difficult=20
> to find the equivalent inductance, capacitance and resistance of the=20
> component with a VNA S21 measurement. Istvan and I have documented=20
> the techniques for doing this in various papers. Be sure and=20
> bias the=20
> component with VDD because the capacitance across the device's power=20
> terminals changes greatly between zero bias and normal bias. =20
> By doing=20
> this, you have measured the chip/package resonance frequency=20
> (sometimes called cut-off) for the component on your board. This=20
> gives you great insight into what you need to do at the PCB level to=20
> provide power to the part. It also tells you what you cannot do (the=20
> frequency beyond which the packaged chip is on it's own).
>=20
> Your other issue has to do with the ability to verify that the PCB=20
> assembly house has actually placed the decoupling capacitors you=20
> specified. This is a tough one. One sure test is to measure the=20
> impedance vs frequency of a sample of assembled boards and see if it=20
> meets the impedance that it was designed to meet. You cannot tell if=20
> individual components are correct but you can tell if the PDS=20
> is going=20
> to be able to meet the power requirements of the power consumers,=20
> which is what you really wanted to know anyway.
>=20
> regards,
> Larry Smith
> Sun Microsystems
>=20
> steve weir wrote:
> > Larry agreed, the problem is that the IC mfgs don't tell us=20
> what their=20
> > networks look like and the resonant frequency shifts with=20
> the external=20
> > L, which in this case is the mounted capacitor array. So,=20
> we are stuck=20
> > shooting in the dark. So, do we throw a bunch of cost at a=20
> problem that=20
> > may or may not be there, and where the cost may or may not yield a=20
> > satisfactory solution?
> >=20
> > As to the significant work that you have done on closely spaced=20
> > resonances I have followed this with great interest, but have some=20
> > exceptions to it, most notably the difficulty auditing the=20
> manufactured=20
> > assembly.
> >=20
> > It is certainly verifiiable that using closely spaced=20
> resonances the=20
> > phase is bound closer to 0, and it is equally verifiable=20
> that this can=20
> > yield fewer components to cross a target Z than would be=20
> necessary by=20
> > the inductance alone. When you are SUN and buy some 100's=20
> millions of=20
> > capacitors per year, there is probably little penalty to=20
> the multitude=20
> > of values, and I suppose you have worked out the manufacturing=20
> > procedures so that they are either auditable or accidents=20
> don't happen=20
> > or both. But, I do not see that as a general case=20
> applicable to small=20
> > and medium size companies.
> >=20
> > Regards,
> >=20
> >=20
> > Steve.
> >=20
> > At 10:30 AM 2/13/2004 -0800, Larry Smith wrote:
> >=20
> >> (I changed the subject to better reflect the content..)
> >>
> >> Craig, Istvan, Steve - "the big V" associated with=20
> discrete capacitor
> >> impedance does not cause ASICs to resonate at the die but it can
> >> certainly make it a lot worse. There will always be some level of
> >> inductance in the mounted package that will resonate with the
> >> capacitance in the die (and/or capacitance on the=20
> package). Depending
> >> on how the PCB capacitors are chosen, their inductance may (and
> >> usually does) add to that of the package and mount . This will
> >> increase the Q of the resonant circuit and lower the resonant
> >> frequency (bad things).
> >>
> >> If PCB capacitors are chosen such that they present a resistive
> >> impedance rather than inductive impedance at the=20
> chip/package resonant
> >> frequency, they provide damping and reduce the Q of the resonant
> >> circuit rather than increase it. This is the best you can=20
> hope for.
> >> The optimum situation is to have the PCB present the=20
> target impedance
> >> at zero phase (resistance) to the resonant circuit. This=20
> presents the
> >> maximum damping resistance with acceptable voltage=20
> regulation (IR drop
> >> in the PDS resistance).
> >>
> >> Sure, it would be nice to have specified ESR capacitors to help us
> >> create the optimum impedance. But I work in a components group.
> >> There is no way we will pay for the added costs, the testing, the
> >> inventory control or deal with the number of unique P/N capacitors
> >> that this would required if there were specified ESR=20
> options for each
> >> capacitor value.
> >>
> >> On the other hand, the ESR of ceramic capacitors available today is
> >> very predictable. For a particular value of capacitor, we=20
> find about
> >> 20% ESR variation over the several major capacitor=20
> suppliers. We can
> >> live with that! By choosing from a menu of 2 dozen or so=20
> capacitors
> >> (three per decade over 5 decades of values) it is easy to=20
> present any
> >> impedance you want to the mounted ASIC including a nice=20
> flat profile
> >> with frequency. In every case that we have evaluated, this has
> >> resulted in the lowest component cost but does create added
> >> manufacturing complexity with more reels of components around the
> >> "pick and place" equipment. Optimize it any way you want! I know
> >> what I am going to do.
> >>
> >> regards,
> >> Larry Smith
> >> Sun Microsystems
> >>
> >> Craig Twardy wrote:
> >> > Steve, Istvan;
> >> > "the big V" can also cause ASICs to resonate at the die.
> >> > Usually the significant lossy component (dampening) is=20
> the ESR of=20
> >> "the big
> >> > V".
> >> > When this gets small, the ASIC package can become underdamped.
> >> > "the big V" does not have to coincident exactly with the natural=20
> >> resonant
> >> > frequency of the ASIC Package.
> >> > It just needs to be somewhere close (within an octave or=20
> two can be
> >> > sufficient).
> >> >
> >> > When this happens the noise seen at the PCB is usually low.
> >> >
> >> > I guess this goes back to a previous thread; without=20
> knowing the ASIC
> >> > package
> >> > And die components, power supply decoupling is a crap shoot.
> >> >
> >> >
> >> >
> >> > Craig
> >> >
> >> > -----Original Message-----
> >> > From: Istvan NOVAK [mailto:istvan.novak@xxxxxxxxxxxxxxxx]
> >> > Sent: February 13, 2004 8:27 AM
> >> > To: weirsp@xxxxxxxxxx
> >> > Cc: si-list@xxxxxxxxxxxxx
> >> > Subject: [SI-LIST] Re: Stack up for EMI reduction,plane=20
> resonance=20
> >> and u-str
> >> > ip radiation etc etc
> >> >
> >> >
> >> > Steve,
> >> >
> >> > Well said. Given the fact that there is still hardly any bypass=20
> >> capacitor
> >> > on the market where the designer would have a known=20
> range for its ESR,
> >> > selecting the largest value cap in a ceramic case style,=20
> and creating a
> >> > single deep V seems to be a good working compromise.
> >> >
> >> > There are two penalties associated with this solution. At low=20
> >> frequencies,
> >> > where the V shape interfaces with the impedance of bigger=20
> >> capacitors, we
> >> > will have to pay a factor of two either in the inductance of the=20
> >> bigger caps
> >> > (need twice as many) or in the capacitance of the ceramic caps=20
> >> creating the
> >> > deep V (if we selected the biggest capacitance in the=20
> case style,=20
> >> this also
> >> > means we need twice as many). There is a similar but=20
> more severe=20
> >> penalty at
> >> > high frequencies, where these ceramic capacitors=20
> interface with the=20
> >> planes,
> >> > let it be thin dielectric -:) or thick dielectric. To=20
> sufficiently=20
> >> suppress
> >> > the capacitor-plane resonance and the first few plane modal=20
> >> resonances, the
> >> > cumulative inductance of the parts has to be several times less,=20
> >> which means
> >> > correspondingly more parts. But I agree that given the=20
> >> circumstances this
> >> > is a safe working solution.
> >> >
> >> > I hope sooner than later the industry will demand bypass=20
> capacitors=20
> >> with
> >> > specified ESR values (with +- tolerance) where the=20
> nominal ESR value=20
> >> can be
> >> > selected from a list, similar to nominal voltage, material, etc.
> >> >
> >> > Regards,
> >> >
> >> > Istvan
> >> >
> >> >
> >> >
> >> > ----- Original Message -----
> >> > From: "steve weir" <weirsp@xxxxxxxxxx>
> >> > To: "Bart Bouma" <bart.bouma@xxxxxxxxx>
> >> > Cc: <si-list@xxxxxxxxxxxxx>; <si-list-bounce@xxxxxxxxxxxxx>;
> >> > <zhang_kun@xxxxxxxxxx>
> >> > Sent: Friday, February 13, 2004 4:47 AM
> >> > Subject: [SI-LIST] Re: Stack up for EMI reduction,plane=20
> resonance=20
> >> and u-str
> >> > ip radiation etc etc
> >> >
> >> >
> >> >
> >> >>Bart, I don't know why people fear that big "V". =20
> Capacitors by the
> >> >>decade are something that I oppose. I have seen people,=20
> including
> >> >>respected consultants mess up capacitors by the decade and blow
> >> >>impedance targets by a factor of 3:1 or more. In the=20
> meantime, no
> >> >>parts were saved. There is nothing wrong with an=20
> impedance lower than
> >> >>target, and the capacitor count is driven by the=20
> requisite inductance
> >> >>to meet the HF intercept. Take the same qty of capacitors using
> >> >>decade spacing, and just substitute the larger value for=20
> all of them
> >> >>and the impedance plot is
> >> >
> >> > still
> >> >
> >> >>very well behaved, and the phase doesn't go all over creation.
> >> >>
> >> >>The only argument that anyone could ever try and make for smaller
> >> >>value capacitors that makes any sense to me is the=20
> higher ESR of the
> >> >>small values, provided it is high enough to get close to=20
> Ztarget that
> >> >>will help damp anti resonance with the planes. In that=20
> case, I can
> >> >>see clear to two values of ceramic caps properly chosen,=20
> but not by
> >> >>the decade. But, I
> >> >
> >> > have
> >> >
> >> >>yet to see any author who advocates multiple values of=20
> MLCCs advocate
> >> >>on the basis of bringing up the ESR. It has always been=20
> based on this
> >> >>folklore surrounding some perceived need for a flat=20
> impedance curve,
> >> >>that many then blow due to antiresonance.
> >> >>
> >> >>Regards,
> >> >>
> >> >>
> >> >>Steve.
> >>
> >>
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