[SI-LIST] Re: Best PDS impedance for package damping
- From: steve weir <weirsp@xxxxxxxxxx>
- To: "Bart Bouma" <bart.bouma@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Mon, 16 Feb 2004 10:23:47 -0800
Bart, that is really only true until you pass the SRF of the last network
capacitor.
An interesting dilemma of the multiple resonance technique is that it takes
more and more of the capacitors as we move up in frequency to keep the
resultant curve under the target line. And if you don't hold phase
significantly closer to zero all the way up to any given frequency cross,
such as IC internals, and the planes, the antiresonant peak remains driven
by the higher combined ESR and ESL of the network, not holding the phase
closer to zero at lower frequencies. Now, for a given capacitor count, and
consequent ESL, we can raise the ESR by using smaller value capacitors to
yield the requisite ESL. The multiresonance approach can actually drive in
the other direction as it seeks to minimize capacitor count, raising ESL,
by using capacitors with low ESR.
The ESR issue is why some authors, like Dr. Johnson have actually advocated
Y5V which under any bias voltage demonstrates a much higher ESR than
"better" dielectrics such as X7R that is relatively immune to voltage.
For example, at 40% bias, a 10V 100nF Y5V is 110mohms, whereas a X7R of the
same rating is 40milliohms.
But even pulling up the ESR can be dubious depending on the impedance the
network that they look into. If it is planes you are interested in taming
and the structure is 4 or 6 layer, the impedance of that network is up in
the ohm range and changing the ESR doesn't show much effect. An IC is
anybody's guess as the vendors don't tell us what is inside their devices,
and do not stipulate an acceptable range of phase. and |Z|.
Did they say that anything is simple?
Regards,
Steve.
At 05:19 PM 2/16/2004 +0100, Bart Bouma wrote:
>Steve and Istvan,
>
>I'm still not convinced (I'm a much too stubborn northener I think: first
>see then believe) :-)
>
>Certainly one of Larry's mails made me think again:
> > The optimum situation is to have the PCB present the target impedance
> > at zero phase (resistance) to the resonant circuit. This presents the
> > maximum damping resistance with acceptable voltage regulation (IR drop
> > in the PDS resistance).
>
>With multiple shallow 'V's' the result will be closer to a zero degree
>situation then with one big deep 'V'.
>
>regards, Bart
>Yageo Europe
>
>
>
>steve weir <weirsp@xxxxxxxxxx>
>
>13-02-04 18:58
>Sent by: si-list-bounce@xxxxxxxxxxxxx
>
>
>Please respond to weirsp
>
> To: "Bart Bouma" <bart.bouma@xxxxxxxxx>
> cc: si-list@xxxxxxxxxxxxx
>si-list-bounce@xxxxxxxxxxxxx
>zhang_kun@xxxxxxxxxx
> Subject: [SI-LIST] Re: Stack up for EMI reduction,plane
> resonance and u-str ip radiation etc etc
> Category:
>
>
>
>Bart, I can see that if you are looking for a flat response that you would
>object to the big "V". However, with current packaging we have a couple of
>realities:
>1) Inductance in a given package is independent of the capacitance
>2) All MLCC capacitors of any size are well past their SRFs at 50MHz and
>beyond
>
>What this leads to is the conclusion that the impedance cross with the IC
>cut-off frequency is going to be inductive, and therefore set by the number
>of capacitors, their package type, and the via attachment method, not by
>the capacitance.
>
>The low frequency cross is either going to be with the VRM for a high
>performance VRM that includes adequate effective resistance, or with a bulk
>capacitor(s). Provided that either is chosen such that the resistive
>impedance is close to, but less than Ztarget, I can readily show that all
>that is left to do is set the minimum capacitance per device for the
>MLCC's. This yields a frequency transition from the bulk to the MLCCs that
>is free of adverse peaking and just dives into the "V". If the capacitance
>is more than that minimum, it just starts the transition early, with a
>higher damping factor.
>
>So, the only argument against the big "V" is that the larger capacitors
>have a lower ESR, and this aggravates peaking with R-L-C's that have higher
>SRF's, namely the planes for EMI, and IC's that may be poorly designed
>and/or specified.
>
>There are things we can do on the EMI front, and as far as the IC's are
>concerned this is an area of considerable frustration due to what seems to
>be negligence among the IC vendors who fail to provide even the most basic
>information about what their devices need to be fed. If an IC vendor wants
>to work in a black box, they should expect to see a PDS that looks
>completely inductive with essentially zero R. If they need something else,
>they need to stipulate it, or as integrators we don't stand a chance.
>
>There is no assurance that any resistive component other than Z target
>itself is adequate to damp a poorly designed and/or specified IC. Even if
>we play capacitors by the decade, or closely spaced resonances as Larry
>Smith and the guys at SUN documented, is there any assurance that we can
>economically get a sufficient ESR * capacitance product to bring peaking
>with an IC down to a particular level.
>
>Regards,
>
>
>Steve.
>
>
>At 12:55 PM 2/13/2004 +0100, Bart Bouma wrote:
>
> >Sorry, former mail was incomplete (I was interrupted by a colleague and
> >afterwards I noticed that mail had been sent accidentally).
> >Finished the example:
> >
> >------------------------------------------------
> >
> >Steve,
> >With the big "V" is nothing wrong, provided that one obtains the required
> >impedance target at all frequencies of interest.
> >In this case the number of caps will be driven by inductance only.
> >Then following will be true:
> >
> > > Take the same qty of capacitors using decade spacing, and just
> > > substitute the larger value for all of them and the impedance plot is
> > still
> > > very well behaved, and the phase doesn't go all over creation.
> >
> >This might be a good approach for large multilayer boards, but - as a
> >RF-guy - I have my doubts about this as the most optimal way.
> >To me it seems that the "staggered tuning" is a better approach (however
> >not necessarely in a 1:10:100: ..... ratio).
> >Combined with low-Q values for the capacitors to iron out the peaks, the
> >result will be quite flat and I think less caps are needed to reach the
> >impedance target.
> >
> >A simple example: (see the figures in the plot I sent you):
> >In order to obtain 100 milliOhm impedance at 200 MHz you will need 10 pcs
> >of 0603-100nF in parallel (ESL = 0.7nH).
> >For reaching the same impedance level with 0603-1nF capacitors, 6 pcs are
> >doing the job although the minimum ESR is many times higher.
> >
> >regards, Bart
> >Yageo Europe
> >
> >
> >
> >
> >Bart, I don't know why people fear that big "V". Capacitors by the decade
> >are something that I oppose. I have seen people, including respected
> >consultants mess up capacitors by the decade and blow impedance targets by
> >a factor of 3:1 or more. In the meantime, no parts were saved.
> >There is nothing wrong with an impedance lower than target, and the
> >capacitor count is driven by the requisite inductance to meet the HF
> >intercept. Take the same qty of capacitors using decade spacing, and just
> >substitute the larger value for all of them and the impedance plot is still
> >very well behaved, and the phase doesn't go all over creation.
> >
> >The only argument that anyone could ever try and make for smaller value
> >capacitors that makes any sense to me is the higher ESR of the small
> >values, provided it is high enough to get close to Ztarget that will help
> >damp anti resonance with the planes. In that case, I can see clear to two
> >values of ceramic caps properly chosen, but not by the decade. But, I have
> >yet to see any author who advocates multiple values of MLCCs advocate on
> >the basis of bringing up the ESR. It has always been based on this
> >folklore surrounding some perceived need for a flat impedance curve, that
> >many then blow due to antiresonance.
> >
> >Regards,
> >
> >
> >Steve.
> >
> >
> >
> >
> >At 10:34 AM 2/13/2004 +0100, Bart Bouma wrote:
> >
> > > > Zhangkun, I am curious, why do you use capacitors as small as
> > 1nF? Do you
> > > > use capacitors spaced by decades, ie: 1uF 100nF, 10nF, 1nF? If
> so, why
> > > > not just use 100nF in an 0603 package? They have the same
> inductance as
> > > > any other value in that package, and with just one value they will not
> > > have
> > > > an antiresonant peak.
> > >
> > >Steve,
> > >you're right. There will be no parallel resonances in that case.
> > >But impedance will not be a 'flat' line over frequency. There will be one
> > >deep dip at the part's resonance frequency which typically will be 20 MHz.
> > >
> > >Using 1nF, 10nF etc. is not a bad idea: it results in a low impedance over
> > >a broad frequency range, with dips at regular intervals.
> > >This is a wellknown method that is used by many people I believe.
> > >By using low-Q parts, the resonance peaks can be controlled.
> > >The 1nF parts are most likely not the best wrt to low ESR values, so are a
> > >good choice I think.
> > >More problematic are e.g. the 100nF 0603 parts, they have a large number
> > >of electrodes and hence a low ESR-figure.
> > >See attached plot: showing three curves for 1nF, 10nF and 100nF 0603
> parts.
> > >(sorry si-listers: attachment will be filtered out).
> > >
> > >best regards, Bart
> > >Yageo Europe
> > >
> > >Re [SI-LIST] Re Stack up for .gif
> > >
> > >
> > >
> > >
> > >steve weir <weirsp@xxxxxxxxxx>
> > >
> > >13-02-04 02:59
> > >Sent by: si-list-bounce@xxxxxxxxxxxxx
> > >
> > >
> > >Please respond to weirsp
> > >
> > > To: zhang_kun@xxxxxxxxxx
> > >si-list@xxxxxxxxxxxxx
> > > cc:
> > > Subject: [SI-LIST] Re: Stack up for EMI reduction,plane
> > > resonance and u-str ip radiation etc etc
> > > Category:
> > >
> > >
> > >
> > >Zhangkun, I am curious, why do you use capacitors as small as 1nF? Do you
> > >use capacitors spaced by decades, ie: 1uF 100nF, 10nF, 1nF? If so, why
> > >not just use 100nF in an 0603 package? They have the same inductance as
> > >any other value in that package, and with just one value they will not
> have
> > >an antiresonant peak.
> > >
> > >Steve.
> > >At 09:42 AM 2/13/2004 +0800, Zhangkun wrote:
> > > >Dear all:
> > > >
> > > >I have reviewed the mails in this thread. The following is my points.
> > > >
> > > >a)From my view, I am caring about the EMI of PCB. Very small common mode
> > > >noise will give rise to critical EMI problem. In my experience, the
> common
> > > >mode noise is proportional to the impedance of power delivery systems.
> > > >This has been verified by measurement and simualtion.
> > > >
> > > >b)I have done some measurement. No matter have many caps are placed
> on the
> > > >boards, the impedance of PDS beyond 200MHz will not get better. It
> should
> > > >be clarified that now I do not use cap less than 1000pF. When the caps
> > > >less than 1000pF is used, there will be a lot of antiresonance. This is
> > > >also verified by simualtion and measurement.
> > > >
> > > >c)I have not studied the interaction between signal in trace and
> noise in
> > > >plane. However, I have treated one case, in which the noise in plane
> > > >seriously affect the signal in trace. After we eliminate the noise in
> > > >plane, the signal become very good.
> > > >
> > > >Best Regards
> > > >
> > > >Zhangkun
> > > >2004.2.13
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